Xilinx MicroBlaze, Reference Manual

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58 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
The MicroBlaze TLB is physically implemented as three separate TLBs:
•
Unified TLB—The UTLB contains 64 entries and is pseudo-associative. Instruction-page and
data-page translation can be stored in any UTLB entry. The initialization and management of
the UTLB is controlled completely by software.
•
Instruction Shadow TLB—The ITLB contains instruction page-translation entries and is fully
associative. The page-translation entries stored in the ITLB represent the most-recently
accessed instruction-page translations from the UTLB. The ITLB is used to minimize
contention between instruction translation and UTLB-update operations. The initialization and
management of the ITLB is controlled completely by hardware and is transparent to software.
•
Data Shadow TLB—The DTLB contains data page-translation entries and is fully associative.
The page-translation entries stored in the DTLB represent the most-recently accessed data-
page translations from the UTLB. The DTLB is used to minimize contention between data
translation and UTLB-update operations. The initialization and management of the DTLB is
controlled completely by hardware and is transparent to software.
Figure 2-19 provides the translation flow for TLB.
Figure 2-19: TLB Address Translation Flow
Generate I-side
Effective Address
Generate D-side
Effective Address
No Translation
Perform ITLB
Look-Up
Perform DTLB
Look-Up
No Translation
Translation Disabled
(MSR[VM]=0)
Translation Enabled
(MSR[VM]=1)
Translation Enabled
(MSR[VM]=1)
Translation Disabled
(MSR[VM]=0)
Perform UTLB
Look-Up
Extract Real
Address from ITLB
Extract Real
Address from DTLB
ITLB Hit ITLB Miss DTLB Miss
DTLB Hit
UTLB Hit UTLB Miss
I-Side TLB Miss
or
D-Side TLB Miss
Exception
Extract Real
Address from UTLB
Route Address
to ITLB
Route Address
to DTLB
Continue I-cache
Access
Continue I-cache
or D-cache
Access
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