MicroBlaze Processor Reference Guide
205
UG081 (v14.7)
Instructions
lbu
Load Byte Unsigned
Description
Loads a byte (8 bits) from the memory location that results from adding the contents of registers rA
and rB. The data is placed in the least significant byte of register rD and the other three bytes in rD
are cleared.
If the R bit is set, a byte reversed memory location is used, loading data with the opposite endianness
of the endianness defined by
C_ENDIANNESS
and the E bit (if virtual protected mode is enabled).
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
Pseudocode
Addr
← (
rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10010;ESR[S]
←
0
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC]
←
10000;ESR[S]
←
0; ESR[DIZ]
←
1
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else
(rD)[24:31]
←
Mem(Addr)
(rD)[0:23]
←
0
Registers Altered
•
rD, unless an exception is generated, in which case the register is unchanged
•
MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
•
ESR[EC], ESR[S], if an exception is generated
•
ESR[DIZ], if a data storage exception is generated
Latency
•
1 cycle with
C_AREA_OPTIMIZED=0
•
2 cycles with
C_AREA_OPTIMIZED=1
Note
The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(
C_USE_REORDER_INSTR = 1
).
lbu
rD, rA, rB
lbur
rD, rA, rB
1 1 0 0 0 0
rD
rA
rB
0 R 0 0 0 0 0 0 0 0 0
0
6
11
16
21
31
