Xilinx MicroBlaze, Reference Manual

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MicroBlaze Processor Reference Guide www.xilinx.com 61
UG081 (v14.7)
Virtual-Memory Management
system software initializes the UTLB with page-translation entries, management of the MicroBlaze
UTLB is usually performed using interrupt handlers running in real mode.
Figure 2-21 diagrams the general process for examining a TLB entry.
The following sections describe the conditions under which exceptions occur due to TLB access
failures.
Data-Storage Exception
When virtual mode is enabled, (MSR[VM]=1), a data-storage exception occurs when access to a
page is not permitted for any of the following reasons:
•
From user mode:
♦
The TLB entry specifies a zone field that prevents access to the page (ZPR[Zn]=00). This
applies to load and store instructions.
♦
The TLB entry specifies a read-only page (TLBLO[WR]=0) that is not otherwise
overridden by the zone field (ZPR[Zn]‚ 11). This applies to store instructions.
Figure 2-21: General Process for Examining a TLB Entry
UG011_41_033101
Check Access
Read TLBLO[RPN]
using TLBHI[SIZE]
TLBHI[V]=1
TLBHI[TID]=0x00
Compare
TLBHI[TID] with PID
Compare
TLBHI[TAG] with EA[EPN]
using TLBHI[SIZE]
Yes
No Yes
Match
Match (TLB Hit)
Check for
Guarded Storage
Instruction Fetch Data Reference
Allowed
Not Guarded
Extract Offset from EA
using TLBHI[SIZE]
Generate Physical Address
from TLBLO[RPN] and Offset
TLB-Entry Miss
No Match
Storage Violation
Guarded
Access Violation
Not Allowed
No
TLB-Entry Miss
TLB-Entry Miss
No Match
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