14
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
Instructions
Instruction Summary
All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A
instructions have up to two source register operands and one destination register operand. Type B
instructions have one source register and a 16-bit immediate operand (which can be extended to 32
bits by preceding the Type B instruction with an imm instruction). Type B instructions have a single
destination register operand. Instructions are provided in the following functional categories:
arithmetic, logical, branch, load/store, and special.
lists the MicroBlaze instruction set.
Chapter 5, MicroBlaze Instruction Set Architecture
for more information on these
instructions.
describes the instruction set nomenclature used in the semantics of each
instruction.
Table 2-5:
Instruction Set Nomenclature
Symbol
Description
Ra
R0 - R31, General Purpose Register, source operand a
Rb
R0 - R31, General Purpose Register, source operand b
Rd
R0 - R31, General Purpose Register, destination operand
SPR[
x
]
Special Purpose Register number
x
MSR
Machine Status Register = SPR[1]
ESR
Exception Status Register = SPR[5]
EAR
Exception Address Register = SPR[3]
FSR
Floating Point Unit Status Register = SPR[7]
PVR
x
Processor Version Register, where
x
is the register number = SPR[8192 +
x
]
BTR
Branch Target Register = SPR[11]
PC
Execute stage Program Counter = SPR[0]
x
[
y
]
Bit
y
of register
x
x
[
y
:
z
]
Bit range
y
to
z
of register
x
x
Bit inverted value of register
x
Imm
16 bit immediate value
Imm
x
x
bit immediate value
FSL
x
4 bit Fast Simplex Link (FSL) or AXI4-Stream port designator, where
x
is the port number
C
Carry flag, MSR[29]
Sa
Special Purpose Register, source operand
Sd
Special Purpose Register, destination operand
s(
x
)
Sign extend argument
x
to 32-bit value
*Addr
Memory contents at location Addr (data-size aligned)
:=
Assignment operator
