Xilinx MicroBlaze, Reference Manual

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256 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5: MicroBlaze Instruction Set Architecture
wdc
Write to Data Cache
Description
Write into the data cache tag to invalidate or flush a cache line. The mnemonic wdc.flush is used to
set the F bit, wdc.clear is used to set the T bit, wdc.ext.flush is used to set the E, F and T bits, and
wdc.ext.clear is used to set the E and T bits.
When C_DCACHE_USE_WRITEBACK is set to 1, the instruction will flush the cache line and
invalidate it if the F bit is set, otherwise it will only invalidate the cache line and discard any data
that has not been written to memory. If the T bit is set, only a cache line with a matching address is
invalidated. Register rA added with rB is the address of the affected cache line. The E bit is not taken
into account.
When C_DCACHE_USE_WRITEBACK is cleared to 0, the instruction will invalidate the cache
line if the E bit is not set. Register rA contains the address of the affected cache line, and the register
rB value is not used. If the E bit is set to 1, MicroBlaze will request that the matching address in an
external cache should be invalidated or flushed, depending on the value of the F bit. The E bit is only
taken into account when the parameter C_INTERCONNECT is set to 3 (ACE).
When MicroBlaze is configured to use an MMU (
C_USE_MMU
>= 1) the instruction is privileged.
This means that if the instruction is attempted in User Mode (
MSR[UM]
= 1) a Privileged Instruction
exception occurs.
Pseudocode
if MSR[UM] = 1 then
ESR[EC]
←
00111
else
if C_DCACHE_USE_WRITEBACK = 1 then
address
←
(Ra) + (Rb)
else
address
←
(Ra)
if E = 0 then
if C_DCACHE_LINE_LEN = 4 then
cacheline_mask
←
(1 << log2(C_DCACHE_BYTE_SIZE) - 4) - 1
cacheline
←
(DCache Line)[(address >> 4)
∧
cacheline_mask]
cacheline_addr
←
address
& 0
xfffffff0
if C_DCACHE_LINE_LEN = 8 then
cacheline_mask
←
(1 << log2(C_DCACHE_BYTE_SIZE) - 5) - 1
cacheline
←
(DCache Line)[(address >> 5)
∧
cacheline_mask]
cacheline_addr
←
address
& 0
xffffffe0
wdc
wdc.flush
wdc.clear
wdc.ext.flush
wdc.ext.clear
rA,rB
rA,rB
rA,rB
rA,rB
rA,rB
1 0 0 1 0 0 0 0 0 0 0 rA rB E 0 0 0 1 1 F 0 1 T 0
0 6 1
1 1
6 2
1 2
7 3
1
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