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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
or
Logical OR
Description
The contents of register rA are ORed with the contents of register rB; the result is placed into
register rD.
Pseudocode
(rD)
←
(rA)
∨
(rB)
Registers Altered
•
rD
Latency
•
1 cycle
Note
The assembler pseudo-instruction nop is implemented as “or r0, r0, r0”.
or
rD, rA, rB
1 0 0 0 0 0
rD
rA
rB
0 0 0 0 0 0 0 0 0 0 0
0
6
1
1
1
6
2
1
3
1