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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
andn
Logical AND NOT
Description
The contents of register rA are ANDed with the logical complement of the contents of register rB;
the result is placed into register rD.
Pseudocode
(rD)
←
(rA)
∧
(rB)
Registers Altered
•
rD
Latency
1 cycle
andn
rD, rA, rB
1 0 0 0 1 1
rD
rA
rB
0 0 0 0 0 0 0 0 0 0 0
0
6
1
1
1
6
2
1
3
1