MicroBlaze Processor Reference Guide
217
UG081 (v14.7)
Instructions
msrset
Read MSR and set bits in MSR
Description
Copies the contents of the special purpose register MSR into register rD. Bit positions in the IMM
value that are 1 are set in the MSR. Bit positions that are 0 in the IMM value are left untouched.
When MicroBlaze is configured to use an MMU (
C_USE_MMU
>= 1) this instruction is privileged
for all IMM values except those only affecting C. This means that if the instruction is attempted in
User Mode (
MSR[UM]
= 1) in this case a Privileged Instruction exception occurs.
With low-latency interrupt mode (
C_USE_INTERRUPT
= 2), the Interrupt_Ack output port is set to
11 if the MSR{IE] bit is set by executing this instruction.
Pseudocode
if MSR[UM] = 1 and IMM
≠
0x4 then
ESR[EC]
←
00111
else
(rD)
←
(MSR)
(MSR)
←
(MSR)
∨
(IMM)
if (IMM) & 2
Interrupt_Ack
←
11
Registers Altered
•
rD
•
MSR
•
ESR[EC], in case a privileged instruction exception is generated
Latency
•
1 cycle
Notes
MSRSET will affect the Carry bit immediately while the remaining bits will take effect one cycle
after the instruction has been executed. When setting the EIP or BIP bit, it is guaranteed that the
processor will not react to any interrupt or normal hardware break for the subsequent instructions.
The value read from MSR may not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect MSR must precede the
MSRSET instruction to guarantee correct MSR value. This applies to both the value copied to
register rD and the changed MSR value itself.
The immediate values has to be less than 2
15
when
C_USE_MMU
>= 1 (User Mode), and less than
2
14
otherwise. Only bits 17 to 31 of the MSR can be set when
C_USE_MMU
>= 1 (User Mode),
and.bits 18 to 31 otherwise.
This instruction is only available when the parameter
C_USE_MSR_INSTR
is set to 1.
msrset
rD, Imm
1 0 0 1 0 1
rD
1 0 0 0 0 0
IMM
0
6
11
16 17
31
