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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
Software Breaks
To perform a software break, use the
brk
and
brki
for detailed information on software breaks.
As a special case, when C_USE_DEBUG is set, and “
brki rD, 0x18”
is executed, a software
breakpoint is signaled to the Xilinx Microprocesor Debugger (XMD) tool, irrespective of the value
of
C_BASE_VECTORS
.
Latency
The time it takes MicroBlaze to enter a break service routine from the time the break occurs depends
on the instruction currently in the execution stage and the latency to the memory storing the break
vector.
Equivalent Pseudocode
r16
←
PC
PC
←
C_BASE_V 0x00000018
MSR[BIP]
←
1
MSR[UMS]
←
MSR[UM], MSR[UM]
←
0, MSR[VMS]
←
MSR[VM], MSR[VM]
←
0
Reservation
←
0
Interrupt
MicroBlaze supports one external interrupt source (connected to the
Interrupt
input port). The
processor only reacts to interrupts if the Interrupt Enable (IE) bit in the Machine Status Register
(MSR) is set to 1. On an interrupt, the instruction in the execution stage completes while the
instruction in the decode stage is replaced by a branch to the interrupt vector. This is either address
C_BASE_VECTORS
+ 0x10, or with low-latency interrupt mode, the address supplied by the
Interrupt Controller.
The interrupt return address (the PC associated with the instruction in the decode stage at the time of
the interrupt) is automatically loaded into general purpose register R14. In addition, the processor
also disables future interrupts by clearing the IE bit in the MSR. The IE bit is automatically set again
when executing the RTID instruction.
Interrupts are ignored by the processor if either of the break in progress (
BIP
) or exception in
progress (
EIP
) bits in the MSR are set to 1.
By using the parameter
C_INTERRUPT_IS_EDGE
, the external interrupt can either be set to level-
sensitive or edge-sensitive:
•
When using level-sensitive interrupts, the
Interrupt
input must remain set until MicroBlaze
has taken the interrupt, and jumped to the interrupt vector. Software must clear the interrupt
before returning from the interrupt handler. If not, the interrupt is taken again, as soon as
interrupts are enabled when returning from the interrupt handler.
•
When using edge-sensitive interrupts, MicroBlaze detects and latches the
Interrupt
input
edge, which means that the input only needs to be asserted one clock cycle. The interrupt input
can remain asserted, but must be deasserted at least one clock cycle before a new interrupt can
be detected. The latching of an edge sensitive interrupt is independent of the IE bit in MSR.
Should an interrupt occur while the IE bit is 0, it will immediately be serviced when the IE bit
is set to 1.
Low-latency Interrupt Mode
A low-latency interrupt mode is available, which allows the Interrupt Controller to directly supply
the interrupt vector for each individual interrupt (via the
Interrupt_Address
input port).
