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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
♦
The data side local memory (DLMB) can only cause instruction bus exception when
C_FAULT_TOLERANT
is set to 1, and either an uncorrectable error occurs in the LMB
memory, as indicated by the
DUE
signal, or
C_ECC_USE_CE_EXCEPTION
is set to 1
and a correctable error occurs in the LMB memory, as indicated by the
DCE
signal. An
error can occur for all read accesses, and for byte and halfword write accesses.
♦
The CacheLink (DXCL) interfaces cannot cause data bus exceptions.
•
Unaligned Exception
The unaligned exception is caused by a word access where the address to the data bus has bits
30 or 31 set, or a half-word access with bit 31 set.
•
Divide Exception
The divide exception is caused by an integer division (idiv or idivu) where the divisor is zero,
or by a signed integer division (idiv) where overflow occurs (-2147483648 / -1).
•
FPU Exception
An FPU exception is caused by an underflow, overflow, divide-by-zero, illegal operation, or
denormalized operand occurring with a floating point instruction.
♦
Underflow occurs when the result is denormalized.
♦
Overflow occurs when the result is not-a-number (NaN).
♦
The divide-by-zero FPU exception is caused by the rA operand to fdiv being zero when rB
is not infinite.
♦
Illegal operation is caused by a signaling NaN operand or by illegal infinite or zero
operand combinations.
•
Privileged Instruction Exception
The Privileged Instruction exception is caused by an attempt to execute a privileged instruction
in User Mode.
•
Stack Protection Violation Exception
A Stack Protection Violation exception is caused by executing a load or store instruction using
the stack pointer (register R1) as rA with an address outside the stack boundaries defined by the
special Stack Low and Stack High registers, causing a stack overflow or a stack underflow.
•
Data Storage Exception
The Data Storage exception is caused by an attempt to access data in memory that results in a
memory-protection violation.
•
Instruction Storage Exception
The Instruction Storage exception is caused by an attempt to access instructions in memory that
results in a memory-protection violation.
•
Data TLB Miss Exception
The Data TLB Miss exception is caused by an attempt to access data in memory, when a valid
Translation Look-Aside Buffer entry is not present, and virtual protected mode is enabled.
•
Instruction TLB Miss Exception
The Instruction TLB Miss exception is caused by an attempt to access instructions in memory,
when a valid Translation Look-Aside Buffer entry is not present, and virtual protected mode is
enabled.
Should an Instruction Bus Exception, Illegal Opcode Exception or Data Bus Exception occur when
C_FAULT_TOLERANT
is set to 1, and an exception is in progress (i.e. MSR[EIP] set and MSR[EE]
cleared), the pipeline is halted, and the external signal
MB_Error
is set.
