16
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
RSUBKC Rd,Ra,Rb
000111
Rd
Ra
Rb
00000000000 Rd := Rb + Ra + C
CMP Rd,Ra,Rb
000101
Rd
Ra
Rb
00000000001 Rd := Rb + Ra + 1
Rd[0] := 0 if (Rb >= Ra) else
Rd[0] := 1
CMPU Rd,Ra,Rb
000101
Rd
Ra
Rb
00000000011 Rd := Rb + Ra + 1 (unsigned)
Rd[0] := 0 if (Rb >= Ra, unsigned) else
Rd[0] := 1
ADDI Rd,Ra,Imm
001000
Rd
Ra
Imm
Rd := s(Imm) + Ra
RSUBI Rd,Ra,Imm
001001
Rd
Ra
Imm
Rd := s(Imm) + Ra + 1
ADDIC Rd,Ra,Imm
001010
Rd
Ra
Imm
Rd := s(Imm) + Ra + C
RSUBIC Rd,Ra,Imm
001011
Rd
Ra
Imm
Rd := s(Imm) + Ra + C
ADDIK Rd,Ra,Imm
001100
Rd
Ra
Imm
Rd := s(Imm) + Ra
RSUBIK Rd,Ra,Imm
001101
Rd
Ra
Imm
Rd := s(Imm) + Ra + 1
ADDIKC Rd,Ra,Imm
001110
Rd
Ra
Imm
Rd := s(Imm) + Ra + C
RSUBIKC Rd,Ra,Imm
001111
Rd
Ra
Imm
Rd := s(Imm) + Ra + C
MUL Rd,Ra,Rb
010000
Rd
Ra
Rb
00000000000 Rd := Ra * Rb
MULH Rd,Ra,Rb
010000
Rd
Ra
Rb
00000000001 Rd := (Ra * Rb) >> 32 (signed)
MULHU Rd,Ra,Rb
010000
Rd
Ra
Rb
00000000011 Rd := (Ra * Rb) >> 32 (unsigned)
MULHSU Rd,Ra,Rb
010000
Rd
Ra
Rb
00000000010 Rd := (Ra, signed * Rb, unsigned) >> 32
(signed)
BSRA Rd,Ra,Rb
010001
Rd
Ra
Rb
01000000000 Rd := s(Ra >> Rb)
BSLL Rd,Ra,Rb
010001
Rd
Ra
Rb
10000000000 Rd := (Ra << Rb) & 0
MULI Rd,Ra,Imm
011000
Rd
Ra
Imm
Rd := Ra * s(Imm)
BSRLI Rd,Ra,Imm
011001
Rd
Ra
00000000000 &
Imm5
Rd : = 0 & (Ra >> Imm5)
BSRAI Rd,Ra,Imm
011001
Rd
Ra
00000010000 &
Imm5
Rd := s(Ra >> Imm5)
BSLLI Rd,Ra,Imm
011001
Rd
Ra
00000100000 &
Imm5
Rd := (Ra << Imm5) & 0
IDIV Rd,Ra,Rb
010010
Rd
Ra
Rb
00000000000 Rd := Rb/Ra
IDIVU Rd,Ra,Rb
010010
Rd
Ra
Rb
00000000010 Rd := Rb/Ra, unsigned
TNEA
GETD Rd,Rb
010011
Rd
00000
Rb
0
N
0
TAE
00000
Rd := FSL Rb[28:31] (data read)
MSR[FSL] := 1 if (FSL_S_Control = 1)
MSR[C] := not FSL_S_Exists if
N
= 1
Table 2-6:
MicroBlaze Instruction Set Summary
(Continued)
Type A
0-5
6-10
11-15 16-20
21-31
Semantics
Type B
0-5
6-10
11-15
16-31