MicroBlaze Processor Reference Guide
199
UG081 (v14.7)
Instructions
get
get from stream interface
Description
MicroBlaze will read from the link x interface and place the result in register rD. If the available
number of links set by
C_FSL_LINKS
is less than or equal to FSLx, link 0 is used.
The get instruction has 32 variants.
The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is
valid. The non-blocking versions will not stall micro blaze and will set carry to ‘0’ if the data was
valid and to ‘1’ if the data was invalid. In case of an invalid access the destination register contents
is undefined.
All data get instructions (when ‘c’ bit is ‘0’) expect the control bit from the interface to be ‘0’. If this
is not the case, the instruction will set MSR[FSL] to ‘1’. All control get instructions (when ‘c’ bit is
‘1’) expect the control bit from the interface to be ‘1’. If this is not the case, the instruction will set
MSR[FSL] to ‘1’.
The exception versions (when ‘e’ bit is ‘1’) will generate an exception if there is a control bit
mismatch. In this case ESR is updated with EC set to the exception cause and ESS set to the link
index. The target register, rD, is not updated when an exception is generated, instead the data is
stored in EDR.
The test versions (when ‘t’ bit is ‘1’) will be handled as the normal case, except that the read signal
to the link is not asserted.
Atomic versions (when ‘a’ bit is ‘1’) are not interruptible. This means that a sequence of atomic
instructions can be grouped together without an interrupt breaking the program flow. However, note
that exceptions may still occur.
When MicroBlaze is configured to use an MMU (
C_USE_MMU
>= 1) and not explicitly allowed by
setting
C_MMU_PRIVILEGED_INSTR
to 1 these instructions are privileged. This means that if
these instructions are attempted in User Mode (
MSR[UM]
=1) a Privileged Instruction exception
occurs.
tnea
get
rD, FSLx
get data from link x
t
= test-only
n
= non-blocking
e
= exception if control bit set
a
= atomic
tne
c
a
get
rD, FSLx
get control from link x
t
= test-only
n
= non-blocking
e
= exception if control bit not set
a
= atomic
0 1 1 0 1 1
rD
0 0 0 0 0 0 n c t a e 0 0 0 0 0 0
FSLx
0
6
11
16
28
31