MicroBlaze Processor Reference Guide
113
UG081 (v14.7)
Local Memory Bus (LMB) Interface Description
:
Data_Write[0:31]
The write data bus is an output from the core and contains the data that is written to memory. It is
valid only when AS is high. Only the byte lanes specified by
Byte_Enable[0:3]
contain valid
data.
AS
The address strobe is an output from the core and indicates the start of a transfer and qualifies the
address bus and the byte enables. It is high only in the first clock cycle of the transfer, after which it
goes low and remains low until the start of the next transfer.
Read_Strobe
The read strobe is an output from the core and indicates that a read transfer is in progress. This signal
goes high in the first clock cycle of the transfer, and may remain high until the clock cycle after
Ready is sampled high. If a new read transfer is directly started in the next clock cycle, then
Read_Strobe
remains high.
Write_Strobe
The write strobe is an output from the core and indicates that a write transfer is in progress. This
signal goes high in the first clock cycle of the transfer, and may remain high until the clock cycle
after Ready is sampled high. If a new write transfer is directly started in the next clock cycle, then
Write_Strobe
remains high.
Data_Read[0:31]
The read data bus is an input to the core and contains data read from memory.
Data_Read
[0:31]
is
valid on the rising edge of the clock when Ready is high.
Ready
The
Ready
signal is an input to the core and indicates completion of the current transfer and that the
next transfer can begin in the following clock cycle. It is sampled on the rising edge of the clock. For
reads, this signal indicates the
Data_Read[0:31]
bus is valid, and for writes it indicates that the
Data_Write[0:31]
bus has been written to local memory.
Table 3-5:
Valid Values for Byte_Enable[0:3]
Byte Lanes Used
Byte_Enable[0:3]
Data[0:7]
Data[8:15]
Data[16:23]
Data[24:31]
0001
0010
0100
1000
0011
1100
1111
