Xilinx MicroBlaze, Reference Manual

Page: 26 / 262

26 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
Special Purpose Registers
Program Counter (PC)
The Program Counter (PC) is the 32-bit address of the execution instruction. It can be read with an
MFS instruction, but it cannot be written with an MTS instruction. When used with the MFS
instruction the PC register is specified by setting Sa = 0x0000.
Figure 2-3 illustrates the PC and
Table 2-8 provides a description and reset value.
Machine Status Register (MSR)
The Machine Status Register contains control and status bits for the processor. It can be read with an
MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry copy. MSR can be
written using either an MTS instruction or the dedicated MSRSET and MSRCLR instructions.
When writing to the MSR using MSRSET or MSRCLR, the Carry bit takes effect immediately and
the remaining bits take effect one clock cycle later. When writing using MTS, all bits take effect one
clock cycle later. Any value written to bit 0 is discarded.
When used with an MTS or MFS instruction, the MSR is specified by setting S x = 0x0001.
Figure 2-4 illustrates the MSR register and Table 2-9 provides the bit description and reset values.
0 31
↑
PC
Figure 2-3: PC
Table 2-8: Program Counter (PC)
Bits Name Description Reset Value
0:31 PC Program Counter
Address of executing instruction, that is, “mfs r2 0” stores
the address of the mfs instruction itself in R2. 0x00000000
0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
CC RESERVED
VMS VM UMS UM
PVR EIP EE DCE DZO ICE FSL BIP C IE RES
Figure 2-4: MSR
Send Feedback