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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3:
MicroBlaze Signal Interface Description
C_ICACHE_ALWAYS_USED
Instruction cache interface
used for all memory
accesses in the cacheable
range
0, 1
0
integer
C_ICACHE_INTERFACE
Instruction cache
CacheLink interface
protocol
0 = IXCL
1 = IXCL2
0, 1
0
yes
3
integer
C_ICACHE_FORCE_TAG_LUTRAM
Instruction cache tag
always implemented with
distributed RAM
0, 1
0
integer
C_ICACHE_STREAMS
Instruction cache streams
0, 1
0
integer
C_ICACHE_VICTIMS
Instruction cache victims
0, 2, 4, 8
0
integer
C_ICACHE_DATA_WIDTH
Instruction cache data
width
0 = 32 bits
1 = Full cache line
2 = 512 bits
0, 1, 2
0
integer
C_ADDR_TAG_BITS
Instruction cache address
tags
0-25
17
yes
integer
C_CACHE_BYTE_SIZE
Instruction cache size
64, 128, 256,
512, 1024,
2048, 4096,
8192, 16384,
32768,
65536
4
8192
integer
C_ICACHE_USE_FSL
Cache over CacheLink
instead of peripheral bus
for instructions
1
1
integer
C_DCACHE_BASEADDR
Data cache base address
0x00000000 -
0xFFFFFFFF
0x0000
0000
std_logic_vector
C_DCACHE_HIGHADDR
Data cache high address
0x00000000 -
0xFFFFFFFF
0x3FFF
FFFF
std_logic_vector
C_USE_DCACHE
Data cache
0, 1
0
integer
C_ALLOW_DCACHE_WR
Data cache write enable
0, 1
1
integer
Table 3-18:
MPD Parameters
(Continued)
Parameter Name
Feature/Description
Allowable
Values
Default
Value
EDK
Tool
Assig
ned
VHDL Type
