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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
The LMB BRAM Interface Controller v3.00.a or later provides the LMB ECC implementation. For
details, including performance and resource utilization, see the
LogiCore IP LMB BRAM Interface
Controller (PG061)
product guide, in the Xilinx EDK IP Documentation.
Instruction and Data Cache Protection
To protect the block RAM in the Instruction and Data Cache, parity is used. When a parity error is
detected, the corresponding cache line is invalidated. This forces the cache to reload the correct
value from external memory. Parity is checked whenever a cache hit occurs.
Note that this scheme only works for write-through, and thus write-back data cache is not available
when fault tolerance is enabled. This is enforced by a DRC.
When new values are written to a block RAM in the cache, parity is also calculated and written. One
parity bit is used for the tag, one parity bit for the instruction cache data, and one parity bit for each
word in a data cache line.
In many cases, enabling fault tolerance does not increase the required number of cache block RAMs,
since spare bits can be used for the parity. Any increase in resource utilization, in particular number
of block RAMs, can easily be seen in the MicroBlaze configuration dialog, when enabling fault
tolerance.
Memory Management Unit Protection
To protect the block RAM in the MMU Unified Translation Look-Aside Buffer (UTLB), parity is
used. When a parity error is detected during an address translation, a TLB miss exception occurs,
forcing software to reload the entry.
When a new TLB entry is written using the TLBHI and TLBLO registers, parity is calculated. One
parity bit is used for each entry.
Parity is also checked when a UTLB entry is read using the TLBHI and TLBLO registers. When a
parity error is detected in this case, the entry is marked invalid by clearing the valid bit.
Enabling fault tolerance does not increase the MMU block RAM size, since a spare bit is available
for the parity.
Branch Target Cache Protection
To protect block RAM in the Branch Target Cache, parity is used. When a parity error is detected
when looking up a branch target address, the address is ignored, forcing a normal branch.
When a new branch address is written to the Branch Target Cache, parity is calculated. One parity
bit is used for each address.
Enabling fault tolerance does not increase the Branch Target Cache block RAM size, since a spare
bit is available for the parity.
Exception Handling
With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface
Controller generates error signals on the LMB interface.
If exceptions are enabled in MicroBlaze, by setting the EE bit in the Machine Status Register, the
uncorrectable error signal either generates an instruction bus exception or a data bus exception,
depending on the affected interface.
Should a bus exception occur when an exception is in progress, MicroBlaze is halted, and the
external error signal
MB_Error
is set. This behavior ensures that it is impossible to execute an
instruction corrupted by an uncorrectable error.
