Xilinx MicroBlaze, Reference Manual

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148 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3: MicroBlaze Signal Interface Description
C_M_AXI_IC_PROTOCOL
Instruction cache AXI
protocol
AXI4 AXI4
string
C_M_AXI_IC_AWUSER_WIDTH
Instruction cache AXI user
width
5 5
integer
C_M_AXI_IC_ARUSER_WIDTH
Instruction cache AXI user
width
5 5
integer
C_M_AXI_IC_WUSER_WIDTH
Instruction cache AXI user
width
1 1
integer
C_M_AXI_IC_RUSER_WIDTH
Instruction cache AXI user
width
1 1
integer
C_M_AXI_IC_BUSER_WIDTH
Instruction cache AXI user
width
1 1
integer
C_M_AXI_IC_USER_VALUE
Instruction cache AXI user
value
0-31 31
integer
C_INTERCONNECT_
M_AXI_IC_READ_ISSUING
Instruction cache AXI read
accesses issued
1,2,4,8 2
yes integer
C_STREAM_INTERCONNECT
Select AXI4-Stream
interconnect
0,1 0
integer
C_Mn_AXIS_PROTOCOL
AXI4-Stream protocol
GENERIC GENERIC
string
C_Sn_AXIS_PROTOCOL
AXI4-Stream protocol
GENERIC GENERIC
string
C_Mn_AXIS_DATA_WIDTH
AXI4-Stream master data
width
32 32
NA integer
C_Sn_AXIS_DATA_WIDTH
AXI4-Stream slave data
width
32 32
NA integer
1. The 7 least significant bits must all be 0.
2. The number of Stream Links (FSL or AXI4) is assigned by the tool itself if you are using the co-processor wizard. If you add the IP manually, you
must update the parameter manually.
3. EDK tool assigned value can be overridden by explicit assignment.
4. Not all sizes are permitted in all architectures. The cache uses between 0 and 32 RAMB primitives (0 if cache size is less than 2048).
5. Not available when
C_AREA_OPTIMIZED
is set to 1.
Table 3-18: MPD Parameters (Continued)
Parameter Name Feature/Description
Allowable
Values
Default
Value
EDK
Tool
Assig
ned
VHDL Type
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