Xilinx MicroBlaze, Reference Manual

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56 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
straightforward than a virtual-mode memory manager. Real mode is often an appropriate solution
for memory management in simple embedded environments, when access-protection is necessary,
but virtual address translation is not required.
Virtual Mode
In virtual mode, the processor translates an effective address into a physical address using the
process shown in
Figure 2-18 . Virtual mode can be enabled by setting the VM bit in the MSR..
Each address shown in Figure 2-18 contains a page-number field and an offset field. The page
number represents the portion of the address translated by the MMU. The offset represents the byte
offset into a page and is not translated by the MMU. The virtual address consists of an additional
field, called the process ID (PID), which is taken from the PID register (see Process-ID Register,
page 36). The combination of PID and effective page number (EPN) is referred to as the virtual page
number (VPN). The value n is determined by the page size, as shown in
Table 2-37 .
System software maintains a page-translation table that contains entries used to translate each
virtual page into a physical page. The page size defined by a page translation entry determines the
size of the page number and offset fields. For example, when a 4 kB page size is used, the page-
number field is 20 bits and the offset field is 12 bits. The VPN in this case is 28 bits.
Then the most frequently used page translations are stored in the translation look-aside buffer
(TLB). When translating a virtual address, the MMU examines the page-translation entries for a
matching VPN (PID and EPN). Rather than examining all entries in the table, only entries contained
in the processor TLB are examined. When a page-translation entry is found with a matching VPN,
the corresponding physical-page number is read from the entry and combined with the offset to form
the 32-bit physical address. This physical address is used by the processor to reference memory.
Figure 2-18: Virtual-Mode Address Translation
UG011_37_021302
32-Bit Effective Address
0
Effective Page Number Offset
n 31
0
PID
24 31
Translation Look-Aside
Buffer (TLB) Look-Up
0
Effective Page Number Offset
n+8 39
PID
8
40-Bit Virtual Address
0
Real Page Number Offset
n 31
32-Bit Physical Address
Process ID Register
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