Xilinx MicroBlaze, Reference Manual

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38 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
Translation Look-Aside Buffer Low Register (TLBLO)
The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation Look-
Aside Buffer (UTLB) entries. It is controlled by the
C_USE_MMU
configuration option on
MicroBlaze. The register is only implemented if
C_USE_MMU
is greater than 1 (User Mode), and
C_AREA_OPTIMIZED
is set to 0. When accessed with the MFS and MTS instructions, the TLBLO
is specified by setting Sa = 0x1003. When reading or writing TLBLO, the UTLB entry indexed by
the TLBX register is accessed. The register is readable according to the memory management
special registers parameter
C_MMU_TLB_ACCESS
.
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBLO entries).
Note:
The UTLB is not reset by the external reset inputs:
Reset
,
MB_Reset
and
Debug_Rst
.
Figure 2-14 illustrates the TLBLO register and Table 2-20 provides bit descriptions and reset
values.
0 22 23 24 28 29 30 31
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
RPN EX WR ZSEL W I M G
Figure 2-14: TLBLO
Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO)
Bits Name Description Reset Value
0:21 RPN Real Page Number or Physical Page Number
When a TLB hit occurs, this field is read from the TLB
entry and is used to form the physical address. Depending
on the value of the SIZE field, some of the RPN bits are
not used in the physical address. Software must clear
unused bits in this field to zero.
Only defined when
C_USE_MMU=3
(Virtual).
Read/Write
0x000000
22 EX Executable
When bit is set to 1, the page contains executable code,
and instructions can be fetched from the page. When bit is
cleared to 0, instructions cannot be fetched from the page.
Attempts to fetch instructions from a page with a clear EX
bit cause an instruction-storage exception.
Read/Write 0
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