Xilinx MicroBlaze, Reference Manual

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34 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
Floating Point Status Register (FSR)
The Floating Point Status Register contains status bits for the floating point unit. It can be read with
an MFS, and written with an MTS instruction. When read or written, the register is specified by
setting Sa = 0x0007. The bits in this register are sticky
−
floating point instructions can only set bits
in the register, and the only way to clear the register is by using the MTS instruction. Figure 2-8
illustrates the FSR register and Table 2-14 provides bit descriptions and reset values.
Exception Data Register (EDR)
The Exception Data Register stores data read on a stream link (FSL or AXI) that caused a stream
exception.
The contents of this register is undefined for all other exceptions. When read with the MFS
instruction, the EDR is specified by setting Sa = 0x000D.
Figure 2-9 illustrates the EDR register and
Table 2-15 provides bit descriptions and reset values.
Note:
The register is only implemented if
C_FSL_LINKS
is greater than 0 and
C_FSL_EXCEPTION
is set to 1.
27 28 29 30 31
↑ ↑ ↑ ↑ ↑ ↑
RESERVED IO DZ OF UF DO
Figure 2-8: FSR
Table 2-14: Floating Point Status Register (FSR)
Bits Name Description Reset Value
0:26 Reserved undefined
27 IO Invalid operation 0
28 DZ Divide-by-zero 0
29 OF Overflow 0
30 UF Underflow 0
31 DO Denormalized operand error 0
0 31
↑
EDR
Figure 2-9: EDR
Table 2-15: Exception Data Register (EDR)
Bits Name Description Reset Value
0:31 EDR Exception Data Register 0x00000000
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