Xilinx MicroBlaze, Reference Manual

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40 www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2: MicroBlaze Architecture
Translation Look-Aside Buffer High Register (TLBHI)
The Translation Look-Aside Buffer High Register is used to access MMU Unified Translation
Look-Aside Buffer (UTLB) entries. It is controlled by the
C_USE_MMU
configuration option on
MicroBlaze. The register is only implemented if
C_USE_MMU
is greater than 1 (User Mode), and
C_AREA_OPTIMIZED
is set to 0. When accessed with the MFS and MTS instructions, the TLBHI
is specified by setting Sa = 0x1004. When reading or writing TLBHI, the UTLB entry indexed by
the TLBX register is accessed. The register is readable according to the memory management
special registers parameter
C_MMU_TLB_ACCESS
.
PID is also used when accessing a TLB entry:
•
When writing TLBHI the value of PID is stored in the TID field of the TLB entry
•
When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBHI entries).
Note:
The UTLB is not reset by the external reset inputs:
Reset
,
MB_Reset
and
Debug_Rst
.
Figure 2-15 illustrates the TLBHI register and Table 2-21 provides bit descriptions and reset values.
0 22 25 26 27 28 31
↑ ↑ ↑ ↑ ↑ ↑
TAG SIZE V E U0
Reserved
Figure 2-15: TLBHI
Table 2-21: Translation Look-Aside Buffer High Register (TLBHI)
Bits Name Description
Reset
Value
0:21 TAG TLB-entry tag
Is compared with the page number portion of the virtual
memory address under the control of the SIZE field.
Read/Write 0x000000
22:24 SIZE Size
Specifies the page size. The SIZE field controls the bit
range used in comparing the TAG field with the page
number portion of the virtual memory address. The page
sizes defined by this field are listed in
Table 2-37 .
Read/Write
000
25 V Valid
When this bit is set to 1, the TLB entry is valid and
contains a page-translation entry.
When cleared to 0, the TLB entry is invalid.
Read/Write 0
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