MicroBlaze Processor Reference Guide
111
UG081 (v14.7)
Processor Local Bus (PLB) Interface Description
Please refer to the
AMBA
®
AXI and ACE Protocol Specification, ARM IHI 0022E
document for
details.
Stream Interfaces
The MicroBlaze AXI4-Stream interfaces (M0_AXIS..M15_AXIS, S0_AXIS..S15_AXIS) are
implemented as 32-bit masters and slaves. Please refer to the
AMBA
®
4 AXI4-Stream Protocol
Specification, Version 1.0, ARM IHI 0051A
document for further details.
The
Mn_AXIS_TLAST
and
Sn_AXIS_TLAST
signals directly correspond to the equivalent
FSLn_M_Control
and
FSLn_S_Control
signals, respectively.
Write Operation
A write to the stream interface is performed by MicroBlaze using one of the put or putd instructions.
A write operation transfers the register contents to an output AXI4 interface. The transfer is
completed in a single clock cycle for blocking mode writes (put and cput instructions) as long as the
interface is not busy. If the interface is busy, the processor stalls until it becomes available. The non-
blocking instructions (with prefix n), always complete in a single clock cycle even if the interface is
busy. If the interface was busy, the write is inhibited and the carry bit is set in the MSR.
Read Operation
A read from the stream interface is performed by MicroBlaze using one of the get or getd
instructions. A read operations transfers the contents of an input AXI4 interface to a general purpose
register. The transfer is typically completed in 2 clock cycles for blocking mode reads as long as data
is available. If data is not available, the processor stalls at this instruction until it becomes available.
In the non-blocking mode (instructions with prefix n), the transfer is completed in one or two clock
cycles irrespective of whether or not data was available. In case data was not available, the transfer
of data does not take place and the carry bit is set in the MSR.
Processor Local Bus (PLB) Interface Description
The MicroBlaze PLB interfaces are implemented as byte-enable capable 32-bit masters. Please refer
to the
IBM 128-Bit Processor Local Bus Architectural Specification (v4.6)
document for details.
M_AXI_DC
M_ACE_DC
C_M_AXI_DC_AWCACHE
Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, exclusive access:
• Normal Non-cacheable Non-bufferable (0010)
C_M_AXI_DC_ARPROT
C_M_AXI_DC_AWPROT
Access Permission:
• Unprivileged, secure data access (000)
C_M_AXI_DC_ARQOS
Quality of Service, read access:
• Priority 12 ((1100)
C_M_AXI_DC_AWQOS
Quality of Service, write access:
• Priority 8 (1000)
Table 3-3:
AXI Interface Signal Definitions
Interface
Signal
Description