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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 4:
MicroBlaze Application Binary Interface
Interrupt and Exception Handling
MicroBlaze assumes certain address locations for handling interrupts and exceptions as indicated in
. At these locations, code is written to jump to the appropriate handlers.
The code expected at these locations is as shown below. For programs compiled without the
-xl-
mode-xmdstub
compiler option, the
crt0.o
initialization file is passed by the
mb-gcc
compiler to the
mb-ld
linker for linking. This file sets the appropriate addresses of the exception
handlers.
For programs compiled with the
-xl-mode-xmdstub
compiler option, the
crt1.o
initialization file is linked to the output program. This program has to be run with the xmdstub
already loaded in the memory at address location 0x0. Hence at run-time, the initialization code in
crt1.o
writes the appropriate instructions to location 0x8 through 0x14 depending on the address
of the exception and interrupt handlers.
The following is code for passing control to Exception and Interrupt handlers, assuming the default
C_BASE_VECTORS
value of 0x00000000:
0x00:
bri _start1
0x04:
nop
0x08:
imm
high bits of address (user exception handler)
0x0c:
bri _exception_handler
0x10:
imm
high bits of address (interrupt handler)
0x14:
bri _interrupt_handler
0x20:
imm
high bits of address (HW exception handler
0x24:
bri _hw_exception_handler
With low-latency interrupt mode, control is directly passed to the interrupt handler for each
individual interrupt utilizing this mode. In this case, it is the responsibility of each handler to save
and restore used registers. The MicroBlaze C compiler (mb-gcc) attribute
fast_interrupt
is
available to allow this task to be performed by the compiler:
void
interrupt_handler_name
() __attribute__((fast_interrupt));
MicroBlaze allows exception and interrupt handler routines to be located at any address location
addressable using 32 bits.
The user exception handler code starts with the label
_exception_handler
, the hardware
exception handler starts with
_hw_exception_handler
, while the interrupt handler code starts
with the label
_interrupt_handler
for interrupts that do not use low-latency handlers.
Table 4-4:
Interrupt and Exception Handling
On
Hardware jumps to
Software Labels
Start / Reset
C_BASE_VECTORS
+ 0x0
_start
User exception
C_BASE_VECTORS
+ 0x8
_exception_handler
Interrupt
C_BASE_VECTORS
+ 0x10
1
1. With low-latency interrupt mode, the vector address is supplied by the Interrupt Controller.
_interrupt_handler
Break (HW/SW)
C_BASE_VECTORS
+ 0x18
-
Hardware exception
C_BASE_VECTORS
+ 0x20
_hw_exception_handler
Reserved by Xilinx for
future use
C_BASE_VECTORS
+ 0x28 -
C_BASE_VECTORS
+ 0x4F
-
