Registers
813
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
19.4.3 SDRAM Timing 1 Register (SDTIM1)
The SDRAM timing 1 register (SDTIM1) configures the SDRAM memory controller to meet many of the
AC timing specification of the SDRAM memory. The SDTIM1 is programmable only when the
TIMUNLOCK bit is set to 1 in the SDRAM configuration register (SDCFG). Note that EMB_CLK is equal to
the period of the EMB_CLK signal. See the SDRAM memory data sheet for information on the appropriate
values to program each field. The SDTIM1 is shown in
and described in
Figure 19-16. SDRAM Timing 1 Register (SDTIM1)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-Ah
R/W-3h
R/W-3h
R/W-1h
15
11
10
6
5
3
2
0
T_RAS
T_RC
T_RRD
Reserved
R/W-7h
R/W-Ah
R/W-2h
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 19-27. SDRAM Timing 1 Register (SDTIM1) Field Descriptions
Bit
Field
Value
Description
31-25
T_RFC
0-7Fh
Specifies the minimum number of EMB_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the t
rfc
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RFC = (t
rfc
/EMB_CLK) - 1
24-22
T_RP
0-7h
Specifies the minimum number of EMB_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the t
rp
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RP = (t
rp
/EMB_CLK) - 1
21-19
T_RCD
0-7h
Specifies the minimum number of EMB_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the t
rcd
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RCD = (t
rcd
/EMB_CLK) - 1
18-16
T_WR
0-7h
Specifies the minimum number of EMB_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the t
wr
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_WR = (t
wr
/EMB_CLK) - 1
When the value of this field is changed from its previous value, the initialization sequence will begin.
15-11
T_RAS
0-1Fh
Specifies the minimum number of EMB_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the t
ras
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RAS = (t
ras
/EMB_CLK) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
0-1Fh
Specifies the minimum number of EMB_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the t
rc
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RC = (t
rc
/EMB_CLK) - 1
5-3
T_RRD
0-7h
Specifies the minimum number of EMB_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the t
rrd
AC timing parameter in the SDRAM data sheet.
Calculate by:
T_RRD = (t
rrd
/EMB_CLK) - 1
Note: for an 8 bank SDRAM device this field must be equal to ((4 × t
RRD
) + (2 × t
CK
)) / (4 × t
CK
) - 1.
2-0
Reserved
0
All writes to these bit(s) must always have a value of 0.