Registers
1308
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Universal Serial Bus OHCI Host Controller
30.3.11 HC Head Bulk Register (HCBULKHEADED)
The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint
descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in
and described in
.
Figure 30-12. HC Head Bulk Register (HCBULKHEADED)
31
16
BHED
R/W-0
15
4
3
0
BHED
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 30-12. HC Head Bulk Register (HCBULKHEADED) Field Descriptions
Bit
Field
Value
Description
31-4
BHED
0-FFF FFFFh Physical address of the head ED on the bulk ED list. This field represents bits 31-4 of the physical
address of the head ED on the bulk ED list. EDs are assumed to begin on a 16-byte aligned
address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see
3-0
Reserved
0
Reserved
30.3.12 HC Current Bulk Register (HCBULKCURRENTED)
The HC current bulk register (HCBULKCURRENTED) defines the physical address of the next endpoint
descriptor (ED) on the bulk ED list. HCBULKCURRENTED is shown in
and described in
.
Figure 30-13. HC Current Bulk Register (HCBULKCURRENTED)
31
16
BCED
R/W-0
15
4
3
0
BCED
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 30-13. HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions
Bit
Field
Value
Description
31-4
BCED
0-FFF FFFFh Physical address of the current ED on the bulk ED list. This field represents bits 31-4 of the
physical address of the next ED on the bulk ED list. EDs are assumed to begin on a 16-byte
aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see
A value of 0 indicates that the USB1.1 host controller has reached the end of the bulk ED list
without finding any transfers to process. This register is automatically updated by the USB1.1 host
controller.
3-0
Reserved
0
Reserved