39
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
27-3.
SPI 4-Pin Option with SPIx_SCS[n]
..................................................................................
27-4.
SPI 4-Pin Option with SPIx_ENA
.....................................................................................
27-5.
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n]
...............................................................
27-6.
Format for Transmitting 12-Bit Word
..................................................................................
27-7.
Format for 10-Bit Received Word
.....................................................................................
27-8.
Clock Mode with POLARITY = 0 and PHASE = 0
..................................................................
27-9.
Clock Mode with POLARITY = 0 and PHASE = 1
..................................................................
27-10. Clock Mode with POLARITY = 1 and PHASE = 0
..................................................................
27-11. Clock Mode with POLARITY = 1 and PHASE = 1
..................................................................
27-12. Five Bits per Character (5-Pin Option)
...............................................................................
27-13. SPI 3-Pin Master Mode with WDELAY
...............................................................................
27-14. SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY
.............................
27-15. SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY
....................................
27-16. SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY
.......................................
27-17. SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY
....................................................
27-18. SPI Global Control Register 0 (SPIGCR0)
...........................................................................
27-19. SPI Global Control Register 1 (SPIGCR1)
...........................................................................
27-20. SPI Interrupt Register (SPIINT0)
......................................................................................
27-21. SPI Interrupt Level Register (SPILVL)
................................................................................
27-22. SPI Flag Register (SPIFLG)
...........................................................................................
27-23. SPI Pin Control Register 0 (SPIPC0)
.................................................................................
27-24. SPI Pin Control Register 1 (SPIPC1)
.................................................................................
27-25. SPI Pin Control Register 2 (SPIPC2)
.................................................................................
27-26. SPI Pin Control Register 3 (SPIPC3)
.................................................................................
27-27. SPI Pin Control Register 4 (SPIPC4)
.................................................................................
27-28. SPI Pin Control Register 5 (SPIPC5)
.................................................................................
27-29. SPI Data Register 0 (SPIDAT0)
.......................................................................................
27-30. SPI Data Register 1 (SPIDAT1)
.......................................................................................
27-31. SPI Buffer Register (SPIBUF)
.........................................................................................
27-32. SPI Emulation Register (SPIEMU)
....................................................................................
27-33. SPI Delay Register (SPIDELAY)
......................................................................................
27-34. Example: t
C2TDELAY
= 8 SPI Module Clock Cycles
....................................................................
27-35. Example: t
T2CDELAY
= 4 SPI Module Clock Cycles
....................................................................
27-36. Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout
...........................................................
27-37. Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout
...........................................................
27-38. SPI Default Chip Select Register (SPIDEF)
.........................................................................
27-39. SPI Data Format Register (SPIFMT
n
)
................................................................................
27-40. SPI Interrupt Vector Register 1 (INTVEC1)
..........................................................................
28-1.
Timer Block Diagram
...................................................................................................
28-2.
Timer Clock Source Block Diagram
...................................................................................
28-3.
64-Bit Timer Mode Block Diagram
....................................................................................
28-4.
Dual 32-Bit Timers Chained Mode Block Diagram
.................................................................
28-5.
Dual 32-Bit Timers Chained Mode Example
.........................................................................
28-6.
Dual 32-Bit Timers Unchained Mode Block Diagram
...............................................................
28-7.
Dual 32-Bit Timers Unchained Mode Example
......................................................................
28-8.
32-Bit Timer Counter Overflow Example
.............................................................................
28-9.
Watchdog Timer Mode Block Diagram
...............................................................................
28-10. Watchdog Timer Operation State Diagram
..........................................................................
28-11. Timer Operation in Pulse Mode (CP
n
= 0)
...........................................................................