18
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
30.3.9
HC Head Control Register (HCCONTROLHEADED)
....................................................
30.3.10
HC Current Control Register (HCCONTROLCURRENTED)
...........................................
30.3.11
HC Head Bulk Register (HCBULKHEADED)
............................................................
30.3.12
HC Current Bulk Register (HCBULKCURRENTED)
....................................................
30.3.13
HC Head Done Register (HCDONEHEAD)
..............................................................
30.3.14
HC Frame Interval Register (HCFMINTERVAL)
.........................................................
30.3.15
HC Frame Remaining Register (HCFMREMAINING)
..................................................
30.3.16
HC Frame Number Register (HCFMNUMBER)
.........................................................
30.3.17
HC Periodic Start Register (HCPERIODICSTART)
.....................................................
30.3.18
HC Low-Speed Threshold Register (HCLSTHRESHOLD)
.............................................
30.3.19
HC Root Hub A Register (HCRHDESCRIPTORA)
......................................................
30.3.20
HC Root Hub B Register (HCRHDESCRIPTORB)
......................................................
30.3.21
HC Root Hub Status Register (HCRHSTATUS)
.........................................................
30.3.22
HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
.....................................
30.3.23
HC Port 2 Status and Control Register (HCRHPORTSTATUS2)
.....................................
31
Universal Serial Bus 2.0 (USB) Controller
..........................................................................
31.1
Introduction
...............................................................................................................
31.1.1
Purpose of the Peripheral
....................................................................................
31.1.2
Features
........................................................................................................
31.1.3
Functional Block Diagram
....................................................................................
31.1.4
Industry Standard(s) Compliance Statement
..............................................................
31.2
Architecture
..............................................................................................................
31.2.1
Clock Control
..................................................................................................
31.2.2
Signal Descriptions
............................................................................................
31.2.3
Indexed and Non-Indexed Registers
.......................................................................
31.2.4
USB PHY Initialization
........................................................................................
31.2.5
VBUS Voltage Sourcing Control
............................................................................
31.2.6
Dynamic FIFO Sizing
.........................................................................................
31.2.7
USB Controller Host and Peripheral Modes Operation
..................................................
31.2.8
Communications Port Programming Interface (CPPI) 4.1 DMA Overview
............................
31.2.9
Test Modes
.....................................................................................................
31.2.10
Reset Considerations
.......................................................................................
31.2.11
Interrupt Support
.............................................................................................
31.2.12
DMA Event Support
.........................................................................................
31.2.13
Power Management
.........................................................................................
31.3
Use Cases
................................................................................................................
31.3.1
User Case 1: Example of How to Initialize the USB Controller
.........................................
31.3.2
User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode
.................
31.3.3
User Case 3: Example of How to Program the USB Endpoints in Host Mode
........................
31.3.4
User Case 4: Example of How to Program the USB DMA Controller
..................................
31.4
Registers
.................................................................................................................
31.4.1
Revision Identification Register (REVID)
...................................................................
31.4.2
Control Register (CTRLR)
....................................................................................
31.4.3
Status Register (STATR)
.....................................................................................
31.4.4
Emulation Register (EMUR)
.................................................................................
31.4.5
Mode Register (MODE)
......................................................................................
31.4.6
Auto Request Register (AUTOREQ)
.......................................................................
31.4.7
SRP Fix Time Register (SRPFIXTIME)
....................................................................
31.4.8
Teardown Register (TEARDOWN)
..........................................................................
31.4.9
USB Interrupt Source Register (INTSRCR)
...............................................................
31.4.10
USB Interrupt Source Set Register (INTSETR)
..........................................................
31.4.11
USB Interrupt Source Clear Register (INTCLRR)
.......................................................
31.4.12
USB Interrupt Mask Register (INTMSKR)
................................................................