a
(WDELAY)
SPIx_CLK
(i)
SPIx_CLK
(ii)
SPIx_CLK
(iii)
SPIx_CLK
(iv)
Case 1
a
(WDELAY)
SPIx_CLK
(i)
SPIx_CLK
(ii)
SPIx_CLK
(iii)
SPIx_CLK
(iv)
Case 2
Architecture
1194
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Serial Peripheral Interface (SPI)
27.2.20 Timing Diagrams
This section contains timing diagrams illustrating the C2TDELAY, C2EDELAY, T2CDELAY, T2EDELAY,
and WDELAY delays and their interaction with the SPIx_SCS[n] and SPIx_ENA pins for all SPI modes.
27.2.20.1 SPI 3-Pin Mode
illustrates the WDELAY option in SPI 3-pin master mode. This is the only delay available in
this mode. In CASE1, a new transfer is initiated during the WDELAY period and the transfer begins
immediately after the WDELAY period ends. In CASE2, while WDELAY has completed, a new transfer will
not begin until SPIDAT0/SPIDAT1 have been written with new data.
Figure 27-13. SPI 3-Pin Master Mode with WDELAY