11
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
21.2.9
Interrupt Support
................................................................................................
21.2.10
EDMA Event Support
.........................................................................................
21.2.11
Power Management
..........................................................................................
21.2.12
Emulation Considerations
....................................................................................
21.3
Registers
...................................................................................................................
21.3.1
Revision Identification Register (REVID)
....................................................................
21.3.2
Power and Emulation Management Register (PWREMU_MGMT)
......................................
21.3.3
GPIO Enable Register (GPIO_EN)
..........................................................................
21.3.4
GPIO Direction 1 Register (GPIO_DIR1)
....................................................................
21.3.5
GPIO Data 1 Register (GPIO_DAT1)
........................................................................
21.3.6
GPIO Direction 2 Register (GPIO_DIR2)
....................................................................
21.3.7
GPIO Data 2 Register (GPIO_DAT2)
........................................................................
21.3.8
Host Port Interface Control Register (HPIC)
................................................................
21.3.9
Host Port Interface Write Address Register (HPIAW)
.....................................................
21.3.10
Host Port Interface Read Address Register (HPIAR)
....................................................
22
Inter-Integrated Circuit (I2C) Module
...................................................................................
22.1
Introduction
................................................................................................................
22.1.1
Purpose of the Peripheral
.....................................................................................
22.1.2
Features
..........................................................................................................
22.1.3
Functional Block Diagram
.....................................................................................
22.1.4
Industry Standard(s) Compliance Statement
................................................................
22.2
Architecture
................................................................................................................
22.2.1
Bus Structure
....................................................................................................
22.2.2
Clock Generation
...............................................................................................
22.2.3
Clock Synchronization
.........................................................................................
22.2.4
Signal Descriptions
.............................................................................................
22.2.5
START and STOP Conditions
................................................................................
22.2.6
Serial Data Formats
............................................................................................
22.2.7
Operating Modes
...............................................................................................
22.2.8
NACK Bit Generation
...........................................................................................
22.2.9
Arbitration
........................................................................................................
22.2.10
Reset Considerations
.........................................................................................
22.2.11
Initialization
.....................................................................................................
22.2.12
Interrupt Support
..............................................................................................
22.2.13
DMA Events Generated by the I2C Peripheral
............................................................
22.2.14
Power Management
..........................................................................................
22.2.15
Emulation Considerations
....................................................................................
22.3
Registers
...................................................................................................................
22.3.1
I2C Own Address Register (ICOAR)
.........................................................................
22.3.2
I2C Interrupt Mask Register (ICIMR)
.........................................................................
22.3.3
I2C Interrupt Status Register (ICSTR)
......................................................................
22.3.4
I2C Clock Divider Registers (ICCLKL and ICCLKH)
.......................................................
22.3.5
I2C Data Count Register (ICCNT)
............................................................................
22.3.6
I2C Data Receive Register (ICDRR)
.........................................................................
22.3.7
I2C Slave Address Register (ICSAR)
........................................................................
22.3.8
I2C Data Transmit Register (ICDXR)
........................................................................
22.3.9
I2C Mode Register (ICMDR)
..................................................................................
22.3.10
I2C Interrupt Vector Register (ICIVR)
......................................................................
22.3.11
I2C Extended Mode Register (ICEMDR)
...................................................................
22.3.12
I2C Prescaler Register (ICPSC)
.............................................................................
22.3.13
I2C Revision Identification Register (REVID1)
............................................................
22.3.14
I2C Revision Identification Register (REVID2)
...........................................................
22.3.15
I2C DMA Control Register (ICDMAC)
......................................................................