Registers
1213
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Serial Peripheral Interface (SPI)
27.3.11 SPI Pin Control Register 5 (SPIPC5)
The SPI pin control register 5 (SPIPC5) is shown in
and described in
Figure 27-28. SPI Pin Control Register 5 (SPIPC5)
31
16
Reserved
R-0
15
12
11
10
9
8
Reserved
SOMICLR
SIMOCLR
CLKCLR
ENACLR
R-0
R/W-0
R/W-0
R/W-0
R/W-0
7
1
0
Reserved
SCS0CLR
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 27-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions
Bit
Field
Value
Description
31-12
Reserved
0
Reads return zero and writes have no effect.
11
SOMICLR
SPIx_SOMI data out clear. This bit is only active when the SPIx_SOMI pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_SOMI pin.
Write 0
No effect.
Write 1
SPIPC3.SOMIDOUT is cleared to 0.
10
SIMOCLR
SPIx_SIMO data out clear. This bit is only active when the SPIx_SIMO pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_SIMO pin.
Write 0
No effect.
Write 1
SPIPC3.SIMODOUT is cleared to 0.
9
CLKCLR
SPIx_CLK data out clear. This bit is only active when the SPIx_CLK pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_CLK pin.
Write 0
No effect.
Write 1
SPIPC3.CLKDOUT is cleared to 0.
8
ENACLR
SPIx_ENA data out clear. This bit is only active when the SPIx_ENA pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_ENA pin.
Write 0
No effect.
Write 1
SPIPC3.ENADOUT is cleared to 0.
7-1
Reserved
0
Reserved
0
SCS0CLR
SPIx_SCS[0] data out clear. This bit is only active when the SPIx_SCS[0] pin is configured as a
general-purpose output pin. Reads return the value of the SPIx_SCS[0] pin.
Write 0
No effect.
Write 1
SPIPC3.SCS0DOUT is cleared to 0.