41
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
30-8.
HC HCAA Address Register (HCHCCA)
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30-9.
HC Current Periodic Register (HCPERIODCURRENTED)
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30-10. HC Head Control Register (HCCONTROLHEADED)
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30-11. HC Current Control Register (HCCONTROLCURRENTED)
......................................................
30-12. HC Head Bulk Register (HCBULKHEADED)
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30-13. HC Current Bulk Register (HCBULKCURRENTED)
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30-14. HC Head Done Register (HCDONEHEAD)
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30-15. HC Frame Interval Register (HCFMINTERVAL)
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30-16. HC Frame Remaining Register (HCFMREMAINING)
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30-17. HC Frame Number Register (HCFMNUMBER)
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30-18. HC Periodic Start Register (HCPERIODICSTART)
.................................................................
30-19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
........................................................
30-20. HC Root Hub A Register (HCRHDESCRIPTORA)
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30-21. HC Root Hub B Register (HCRHDESCRIPTORB)
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30-22. HC Root Hub Status Register (HCRHSTATUS)
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30-23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
.................................................
30-24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2)
.................................................
31-1.
Functional Block Diagram
..............................................................................................
31-2.
USB Clocking Diagram
.................................................................................................
31-3.
Interrupt Service Routine Flow Chart
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31-4.
CPU Actions at Transfer Phases
......................................................................................
31-5.
Sequence of Transfer
...................................................................................................
31-6.
Service Endpoint 0 Flow Chart
........................................................................................
31-7.
IDLE Mode Flow Chart
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31-8.
TX Mode Flow Chart
....................................................................................................
31-9.
RX Mode Flow Chart
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31-10. Setup Phase of a Control Transaction Flow Chart
..................................................................
31-11. IN Data Phase Flow Chart
.............................................................................................
31-12. OUT Data Phase Flow Chart
..........................................................................................
31-13. Completion of SETUP or OUT Data Phase Flow Chart
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31-14. Completion of IN Data Phase Flow Chart
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31-15. USB Controller Block Diagram
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31-16. Host Packet Descriptor Layout
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31-17. Host Buffer Descriptor Layout
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31-18. Teardown Descriptor Layout
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31-19. Relationship Between Memory Regions and Linking RAM
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31-20. High-Level Transmit and Receive Data Transfer Example
........................................................
31-21. Transmit Descriptors and Queue Status Configuration
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31-22. Transmit USB Data Flow Example (Initialization)
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31-23. Transmit USB Data Flow Example (Completion)
...................................................................
31-24. Receive Descriptors and Queue Status Configuration
.............................................................
31-25. Receive USB Data Flow Example (Initialization)
....................................................................
31-26. Receive USB Data Flow Example (Completion)
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31-27. Revision Identification Register (REVID)
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31-28. Control Register (CTRLR)
..............................................................................................
31-29. Status Register (STATR)
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31-30. Emulation Register (EMUR)
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31-31. Mode Register (MODE)
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31-32. Auto Request Register (AUTOREQ)
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