Registers
814
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
19.4.4 SDRAM Timing 2 Register (SDTIM2)
Like SDRAM timing 1 register (SDTIM1), the SDRAM timing register 2 (SDTIM2) also configures the
SDRAM memory controller to meet the AC timing specification of the SDRAM memory. The SDTIM2 is
programmable only when the TIMUNLOCK bit is set to 1 in the SDRAM configuration register (SDCFG).
Note that EMB_CLK is equal to the period of the EMB_CLK signal. See the SDRAM data sheet for
information on the appropriate values to program each field. SDTIM2 is shown in
and
described in
Figure 19-17. SDRAM Timing 2 Register (SDTIM2)
31
30
27
26
23
22
16
Rsvd
T_RAS_MAX
Reserved
T_XSR
R-0
R/W-Eh
R-0
R/W-Ah
15
5
4
0
Reserved
T_CKE
R/W-0
R/W-7h
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 19-28. SDRAM Timing 2 Register (SDTIM2) Field Descriptions
Bit
Field
Value
Description
31
Reserved
0
All writes to these bit(s) must always have a value of 0.
30-27
T_RAS_MAX
0-Fh
Maximum number of refresh_rate intervals from Activate to Precharge command.
26-23
Reserved
0
All writes to these bit(s) must always have a value of 0.
22-16
T_XSR
0-7Fh
Minimum number of EMB_CLK cycles from Self-Refresh exit to any command other than a Read
command, minus one. This field must satisfy t
XSR
for the SDRAM device.
T_XSR = (t
xsr
/EMIF_CLK) - 1
15-5
Reserved
0
All writes to these bit(s) must always have a value of 0.
4-0
T_CKE
0-1Fh
Minimum number of EMB_CLK cycles between EMB_SDCKE changes, minus one. This field must
satisfy t
RAS
for the SDRAM device.
T_CKE = (t
ras
/EMIF_CLK) - 1