Example Configuration
750
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface A (EMIFA)
18.3.2.3.2 Meeting AC Timing Requirements for NAND Flash
When configuring the EMIFA to interface to NAND Flash, you must consider the AC timing requirements
of the NAND Flash as well as the AC timing requirements of the EMIFA. These can be found in the data
sheet for each respective device. The read and write asynchronous cycles are programmed separately in
the asynchronous configuration register (CE
n
CFG).
A NAND Flash access cycle is composed of a command, address, and data phases. The EMIFA will not
automatically generate these three phases to complete a NAND access with one transfer request. To
complete a NAND access cycle, multiple single asynchronous access cycles must be completed by the
EMIFA. The command and address phases of a NAND Flash access cycle are asynchronous writes
performed by the EMIFA where as the data phase can be either an asynchronous write or a read
depending on whether the NAND Flash is being programmed or read.
Therefore, to determine the required EMIFA configuration to interface to the NAND Flash for a read
operation,
and
list the AC timing parameters that must be considered.
Table 18-41. EMIFA Read Timing Requirements
Parameter
Description
t
SU
Data Setup time, data valid before EMA_OE high
t
H
Data Hold time, data valid after EMA_OE high
Table 18-42. NAND Flash Read Timing Requirements
Parameter
Description
t
RP
Read Pulse width
t
REA
Read Enable Access time
t
CEA
Chip Enable low to output valid
t
CHZ
Chip Enable high to output High-Z
t
RC
Read Cycle time
t
RHZ
Read enable high to output High-Z
t
CLR
Command Latch low to Read enable low
shows an asynchronous read access and describes how the EMIFA and NAND Flash AC
timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.