SYSCLK2
SYSCLK5
DIV4P5 CLK
PLL Controller
0
1
CFGCHIP3[EMB_CLKSRC]
LPSC #6
0001
0010
CLK1
CLK2
VCLK
MCLK
SDRAM_IN_CLK
EMIFB
PINMUX0[15:12]
EMB_CLK
Signal
On Chip
Peripheral Clocking
110
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Device Clocking
Figure 6-3. EMIFB Clocking Diagram
(1)
See
for an explanation of POSTDIV divider modes.
Table 6-5. EMIFB MCLK Frequencies
OSCIN
Frequency
PLL Multiplier
Register
Setting
Multiplier
Frequency
(MHz)
Post Divider
Mode
(1)
POSTDIV
Output
Frequency
DIV4P5
PLLDIV5
Register
Setting
SYSCLK5
25
24
600
Div2
300 MHz
133 MHz
2
100 MHz
Div3
200 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
25
18
450
Div2
225 MHz
100 MHz
2
75 MHz
1
112.5 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
25
16
400
Div2
200 MHz
89 MHz
2
66.6 MHz
1
100 MHz
Div3
133 MHz
89 MHz
0
133 MHz
Div4
100 MHz
89 MHz
0
133 MHz