PSC Interrupts
146
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Power and Sleep Controller (PSC)
8.5.1.1
Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTAT
n
. In particular, a power
domain emulation event occurs under the following conditions:
•
When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
•
When force power is asserted by emulation and power domain is not already in the on state
•
When force active is asserted by emulation and power domain is not already in the on state
NOTE:
Putting the pseudo/RAM power domain associated with DSP (PD_DSP) to off state is
currently
not
supported.
8.5.1.2
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTAT
n
). In particular, a module state emulation event
occurs under the following conditions:
•
When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
•
When force active is asserted by emulation and module is not already in the enable state
8.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTAT
n
). In particular, a module local reset emulation
event occurs under the following conditions:
•
When assert reset is asserted by emulation although software de-asserted the local reset
•
When wait reset is asserted by emulation
•
When block reset is asserted by emulation and software attempts to change the state of local reset
8.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTL
n
(where n is the modules that have IcePick emulation support, as specified in
).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled in the DSP interrupt controller. For details on the DSP
interrupt controller, see the
DSP Subsystem
chapter.
The PSC interrupt status bits are:
•
For DSP:
–
The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
–
The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
–
The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.