PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
DIV4.5
1
0
EMIFA
Internal
Clock
Source
CFGCHIP3[EMA_CLKSRC]
DIV4.5
EMIFB
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
1
0
Pre-Div
PLLM
PLLEN
AUXCLK
0
1
PLL
Post-Div
CLKMODE
1
0
Square
Wave
Crystal
OSCIN
OBSCLK Pin
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
OCSEL[OCSRC]
OSCDIV
(A)
PLL0 Control
117
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
Figure 7-1. PLL0 Structure
A
This register is not supported on the C6745 DSP.