Architecture
470
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.2.9.2 EDMA3 Interrupt Servicing
On completion of a transfer (early or normal completion), the EDMA3 channel controller sets the
appropriate bit in the interrupt pending register (IPR) as specified by the transfer completion codes. If the
completion interrupts are appropriately enabled, then the CPU enters the interrupt service routine (ISR)
when the completion interrupt is asserted. Since there is a single completion interrupt for all DMA/QDMA
channels.
After servicing the interrupt, the ISR should clear the corresponding bit in IPR; therefore, enabling
recognition of future interrupts. Only when all IPR bits are cleared, the EDMA3CC will assert additional
completion interrupts.
It is possible that when one interrupt is serviced; many other transfer completions result in additional bits
being set in IPR, thereby resulting in additional interrupts. It is likely that each of these bits in IPR would
need different types of service; therefore, the ISR must check all pending interrupts and continue until all
the posted interrupts are appropriately serviced.
Following are examples (pseudo code) for a CPU interrupt service routine for an EDMA3CC completion
interrupt.
The ISR routine in
is more exhaustive and incurs a higher latency.
Example 16-2. Interrupt Servicing
The pseudo code:
1. Read the interrupt pending register (IPR).
2. Perform the operations needed.
3. Write to the interrupt pending clear register (ICR) to clear the corresponding IPR bit.
4. Read IPR again:
(a) If IPR is not equal to 0, repeat from step 2 (implies occurrence of new event between step 2 to step 4).
(b) If IPR is equal to 0, this should assure you that all enabled interrupts are inactive.
NOTE:
It is possible that during step 4, an event occurs while the IPR bits are read to be 0 and the
application is still in the interrupt service routine. If this happens, a new interrupt is recorded in
the device interrupt controller and a new interrupt is generated as soon as the application exits
the interrupt service routine.