Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2
SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(3)
DMA
Peripherals
Display
Internal Memory
LCD
Ctlr
128KB
RAM
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI
MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
GPIO
PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
RTC/
32-kHz
OSC
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
Introduction
67
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Overview
TMS320C6747 DSP Block Diagram
Note: Not all peripherals are available at the same time due to multiplexing.