Registers
1212
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Serial Peripheral Interface (SPI)
27.3.10 SPI Pin Control Register 4 (SPIPC4)
The SPI pin control register 4 (SPIPC4) is shown in
and described in
Figure 27-27. SPI Pin Control Register 4 (SPIPC4)
31
16
Reserved
R-0
15
12
11
10
9
8
Reserved
SOMISET
SIMOSET
CLKSET
ENASET
R-0
R/W-0
R/W-0
R/W-0
R/W-0
7
1
0
Reserved
SCS0SET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 27-18. SPI Pin Control Register 4 (SPIPC4) Field Descriptions
Bit
Field
Value
Description
31-12
Reserved
0
Reads return zero and writes have no effect.
11
SOMISET
SPIx_SOMI data out set. This bit is only active when the SPIx_SOMI pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_SOMI pin.
Write 0
No effect
Write 1
SPIPC3.SOMIDOUT is set to 1.
10
SIMOSET
SPIx_SIMO data out set. This bit is only active when the SPIx_SIMO pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_SIMO pin.
Write 0
No effect
Write 1
SPIPC3.SIMODOUT is set to 1.
9
CLKSET
SPIx_CLK data out set. This bit is only active when the SPIx_CLK pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_CLK pin.
Write 0
No effect
Write 1
SPIPC3.CLKDOUT is set to 1.
8
ENASET
SPIx_ENA data out set. This bit is only active when the SPIx_ENA pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_ENA pin.
Write 0
No effect.
Write 1
SPIPC3.ENADOUT is set to 1.
7-1
Reserved
0
Reserved
0
SCS0SET
SPIx_SCS[0] data out set. This bit is only active when the SPIx_SCS[0] pin is configured as a general-
purpose output pin. Reads return the value of the SPIx_SCS[0] pin.
Write 0
No effect
Write 1
SPIPC3.SCS0DOUT is set to 1.