Architecture
805
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
LPSC Sync Reset
Sync reset of EMIFB through LPSC doesn't reset the EMIFB registers or memory. Thus EMIFB LPSC
sync reset acts similar to EMIFB LPSC disable. Following is the procedure to put EMIFB in sync reset
state
•
EMIFB should be put to self-refresh mode before stopping the clock. Refer to
for
details on self-refresh mode. The EMIFB memory controller will complete any outstanding accesses
and backlogged refresh cycles and then place the EMIFB memory controller in self-refresh mode.
•
To enable clock stopping, MCLKSTOP_EN bit in SDRFC must be set to 1. Refer to
for
details.
•
Then, program the LPSC of EMIFB to reset state.
On sync reset, requests to EMIFB are not honored. To bring EMIFB back to enable state, use the enable
procedure described in
19.2.10 Emulation Considerations
The EMIFB memory controller remains fully functional during emulation halts, to allow emulation access to
external memory.
19.3 Example Configuration
The EMIFB memory controller allows a high degree of programmability for shaping SDRAM accesses.
The programmability inherent to the EMIFB memory controller provides the EMIFB memory controller with
the flexibility to interface with a variety of SDRAM devices. By programming the SDRAM configuration
register (SDCFG), SDRAM refresh control register (SDRFC), SDRAM timing register 1 (SDTIM1), and
SDRAM timing register 2 (SDTIM2), the EMIFB memory controller can be configured to meet the data
sheet specification for JESD21-C compliant SDR SDRAM. This section presents an example describing
how to interface the EMIFB memory controller to a JESD21-C SDR SDRAM 64MB device. The EMIFB
memory controller is assumed to be operating at 133 MHz.
Hardware Configuration
The following figures show how to connect the EMIFB memory controller to an SDR SDRAM device.
displays a 32-bit interface; therefore, two 16-bit SDR SDRAM devices are connected to the
EMIFB memory controller. From
, you can see that the data bus and data mask (byte enable)
signals are point-to-point where as all other address, control, and clocks are not.
displays a
16-bit interface; therefore, all signals are point-to-point.
Software Configuration
Four memory-mapped registers must be programmed to configure the EMIFB memory controller to meet
the data sheet specification of the attached SDR SDRAM device. The registers are:
•
SDRAM configuration register (SDCFG)
•
SDRAM refresh control register (SDRFC)
•
SDRAM timing register 1 (SDTIM1)
•
SDRAM timing register 2 (SDTIM2)
The following sections describe how to configure each of these registers. See
for more
information on the EMIFB memory controller registers.
PLL Programming for EMIFB
The device PLL Controller should first be programmed to select the desired EMB_CLK frequency. Before
doing this, the SDRAM should be placed into Self-Refresh Mode by setting the SR_PD bit and LP_MODE
bit in SDRFC to 0 and 1, respectively. The EMB_CLK frequency can now be adjusted to the desired value
by programming the appropriate SYSCLK domain of the PLL Controller. Once the PLL has been
reprogrammed, remove the SDRAM from Self-Refresh by clearing the LP_MODE bit in SDRFC.