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Example Configuration

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SPRUH91D – March 2013 – Revised September 2016

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Copyright © 2013–2016, Texas Instruments Incorporated

External Memory Interface A (EMIFA)

Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
are equal to EMIFA clock cycles minus 1 cycle, the CE3CFG should be configured as in

. In

this example, the EMA_WAIT signal is not implemented; therefore, the asynchronous wait cycle
configuration register (AWCC) does not need to be programmed.

Table 18-39. Configuring CE3CFG for TC5516100FT-12 Example

Parameter

Setting

SS

Select Strobe mode.

• SS = 0. Places EMIFA in Normal Mode.

EW

Extended Wait mode enable.

• EW = 0. Disabled Extended wait mode.

W_SETUP/R_SETUP

Read/Write setup widths.

• W_SETUP = 0

• R_SETUP = 0

W_STROBE/R_STROBE

Read/Write strobe widths.

• W_STROBE = 0

• R_STROBE = 0

W_HOLD/R_HOLD

Read/Write hold widths.

• W_HOLD = 0

• R_HOLD = 0

TA

Minimum turnaround time.

• TA = 0

ASIZE

Asynchronous Device Bus Width.

• ASIZE = 1, select a 16-bit data bus width

18.3.2.3 Interfacing to NAND Flash

The following example explains how to interface the EMIFA to the Hynix HY27UA081G1M NAND Flash
device.

18.3.2.3.1 Margin Requirements

The Flash interface is typically a low-performance interface compared to synchronous memory interfaces,
high-speed asynchronous memory interfaces, and high-speed FIFO interfaces. For this reason, this
example gives little attention to minimizing the amount of margin required when programming the
asynchronous timing parameters. The approach used requires approximately 10 ns of margin on all
parameters, which is not significant for a 100-ns read or write cycle. For additional details on minimizing
the amount of margin, see the ASRAM example given in

Section 18.3.2.2

Table 18-40. Recommended Margins

Timing Parameter

Recommended Margin

Output Setup

10 nS

Output Hold

10 nS

Input Setup

10 nS

Input Hold

10 nS

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Summary of Contents for TMS320C6745 DSP

Page 1: ...TMS320C6745 C6747 DSP Technical Reference Manual Literature Number SPRUH91D March 2013 Revised September 2016 ...

Page 2: ...1 Introduction 83 5 1 1 Purpose of the MPU 83 5 1 2 Features 83 5 1 3 Block Diagram 83 5 1 4 MPU Default Configuration 84 5 2 Architecture 84 5 2 1 Privilege Levels 84 5 2 2 Memory Protection Ranges 85 5 2 3 Permission Structures 86 5 2 4 Protection Check 87 5 2 5 DSP L1 L2 Cache Controller Accesses 87 5 2 6 MPU Register Protection 87 5 2 7 Invalid Accesses and Exceptions 88 5 2 8 Reset Considerat...

Page 3: ... 122 7 4 2 Reset Type Status Register RSTYPE 122 7 4 3 PLL Control Register PLLCTL 123 7 4 4 OBSCLK Select Register OCSEL 124 7 4 5 PLL Multiplier Control Register PLLM 125 7 4 6 PLL Pre Divider Control Register PREDIV 125 7 4 7 PLL Controller Divider 1 Register PLLDIV1 126 7 4 8 PLL Controller Divider 2 Register PLLDIV2 126 7 4 9 PLL Controller Divider 3 Register PLLDIV3 127 7 4 10 PLL Controller...

Page 4: ...2 Power Domain 1 Status Register PDSTAT1 156 8 6 13 Power Domain 0 Control Register PDCTL0 157 8 6 14 Power Domain 1 Control Register PDCTL1 158 8 6 15 Power Domain 0 Configuration Register PDCFG0 159 8 6 16 Power Domain 1 Configuration Register PDCFG1 160 8 6 17 Module Status n Register MDSTATn 161 8 6 18 PSC0 Module Control n Register modules 0 15 MDCTLn 162 8 6 19 PSC1 Module Control n Register...

Page 5: ...mable Real Time Unit Subsystem PRUSS 241 13 Enhanced Capture eCAP Module 243 13 1 Introduction 244 13 1 1 Purpose of the Peripheral 244 13 1 2 Features 244 13 2 Architecture 245 13 2 1 Capture and APWM Operating Mode 246 13 2 2 Capture Mode Description 247 13 3 Applications 254 13 3 1 Absolute Time Stamp Operation Rising Edge Trigger Example 255 13 3 2 Absolute Time Stamp Operation Rising and Fall...

Page 6: ...C Converter 363 14 3 9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter 368 14 4 Registers 371 14 4 1 Time Base Submodule Registers 371 14 4 2 Counter Compare Submodule Registers 375 14 4 3 Action Qualifier Submodule Registers 378 14 4 4 Dead Band Generator Submodule Registers 382 14 4 5 PWM Chopper Submodule Register 385 14 4 6 Trip Zone Submodule Registers 386 14 4 7 Event Trigger S...

Page 7: ... 2 Features 437 16 1 3 Functional Block Diagram 439 16 1 4 Terminology Used in This Document 439 16 2 Architecture 441 16 2 1 Functional Overview 441 16 2 2 Types of EDMA3 Transfers 444 16 2 3 Parameter RAM PaRAM 447 16 2 4 Initiating a DMA Transfer 457 16 2 5 Completion of a DMA Transfer 460 16 2 6 Event Channel and PaRAM Mapping 461 16 2 7 EDMA3 Channel Controller Regions 464 16 2 8 Chaining EDM...

Page 8: ...Node Priority 608 17 2 14 Reset Considerations 609 17 2 15 Initialization 610 17 2 16 Interrupt Support 612 17 2 17 Power Management 616 17 2 18 Emulation Considerations 616 17 3 Registers 617 17 3 1 EMAC Control Module Registers 617 17 3 2 MDIO Registers 631 17 3 3 EMAC Module Registers 644 18 External Memory Interface A EMIFA 694 18 1 Introduction 695 18 1 1 Purpose of the Peripheral 695 18 1 2 ...

Page 9: ... Register 3 NAND4BITECC3 778 18 4 19 NAND Flash 4 Bit ECC Register 4 NAND4BITECC4 778 18 4 20 NAND Flash 4 Bit ECC Error Address Register 1 NANDERRADD1 779 18 4 21 NAND Flash 4 Bit ECC Error Address Register 2 NANDERRADD2 779 18 4 22 NAND Flash 4 Bit ECC Error Value Register 1 NANDERRVAL1 780 18 4 23 NAND Flash 4 Bit ECC Error Value Register 2 NANDERRVAL2 780 19 External Memory Interface B EMIFB 7...

Page 10: ...Registers 834 20 3 1 Revision ID Register REVID 835 20 3 2 GPIO Interrupt Per Bank Enable Register BINTEN 836 20 3 3 GPIO Direction Registers DIRn 837 20 3 4 GPIO Output Data Registers OUT_DATAn 839 20 3 5 GPIO Set Data Registers SET_DATAn 841 20 3 6 GPIO Clear Data Registers CLR_DATAn 843 20 3 7 GPIO Input Data Registers IN_DATAn 845 20 3 8 GPIO Set Rising Edge Interrupt Registers SET_RIS_TRIGn 8...

Page 11: ... 22 2 Architecture 893 22 2 1 Bus Structure 893 22 2 2 Clock Generation 894 22 2 3 Clock Synchronization 895 22 2 4 Signal Descriptions 895 22 2 5 START and STOP Conditions 896 22 2 6 Serial Data Formats 897 22 2 7 Operating Modes 899 22 2 8 NACK Bit Generation 900 22 2 9 Arbitration 901 22 2 10 Reset Considerations 902 22 2 11 Initialization 902 22 2 12 Interrupt Support 903 22 2 13 DMA Events Ge...

Page 12: ...and LIDD_CS1_ADDR 958 23 3 7 LCD LIDD CSn Data Read Write Registers LIDD_CS0_DATA and LIDD_CS1_DATA 959 23 3 8 LCD Raster Control Register RASTER_CTRL 960 23 3 9 LCD Raster Timing Register 0 RASTER_TIMING_0 967 23 3 10 LCD Raster Timing Register 1 RASTER_TIMING_1 969 23 3 11 LCD Raster Timing Register 2 RASTER_TIMING_2 973 23 3 12 LCD Raster Subpanel Display Register RASTER_SUBPANEL 977 23 3 13 LC...

Page 13: ...ACLKXCTL 1077 24 1 30 Transmit High Frequency Clock Control Register AHCLKXCTL 1078 24 1 31 Transmit TDM Time Slot Register XTDM 1079 24 1 32 Transmitter Interrupt Control Register XINTCTL 1080 24 1 33 Transmitter Status Register XSTAT 1081 24 1 34 Current Transmit TDM Time Slot Register XSLOT 1082 24 1 35 Transmit Clock Check Control Register XCLKCHK 1083 24 1 36 Transmitter DMA Event Control Reg...

Page 14: ... 1123 25 4 Registers 1124 25 4 1 MMC Control Register MMCCTL 1125 25 4 2 MMC Memory Clock Control Register MMCCLK 1126 25 4 3 MMC Status Register 0 MMCST0 1127 25 4 4 MMC Status Register 1 MMCST1 1129 25 4 5 MMC Interrupt Mask Register MMCIM 1130 25 4 6 MMC Response Time Out Register MMCTOR 1132 25 4 7 MMC Data Read Time Out Register MMCTOD 1133 25 4 8 MMC Block Length Register MMCBLEN 1134 25 4 9...

Page 15: ... 26 3 14 Control Register CTRL 1164 26 3 15 Status Register STATUS 1165 26 3 16 Interrupt Register INTERRUPT 1166 26 3 17 Compensation LSB Register COMPLSB 1167 26 3 18 Compensation MSB Register COMPMSB 1168 26 3 19 Oscillator Register OSC 1169 26 3 20 Scratch Registers SCRATCH0 SCRATCH2 1170 26 3 21 Kick Registers KICK0R KICK1R 1170 27 Serial Peripheral Interface SPI 1171 27 1 Introduction 1172 2...

Page 16: ...28 64 Bit Timer Plus 1226 28 1 Introduction 1227 28 1 1 Purpose of the Peripheral 1227 28 1 2 Features 1227 28 1 3 Block Diagram 1228 28 1 4 Industry Standard Compatibility Statement 1228 28 1 5 Architecture General Purpose Timer Mode 1228 28 1 6 Architecture Watchdog Timer Mode 1240 28 1 7 Reset Considerations 1242 28 1 8 Interrupt Support 1242 28 1 9 DMA Event Support 1242 28 1 10 TM64P_OUT Even...

Page 17: ...29 3 8 Line Status Register LSR 1284 29 3 9 Modem Status Register MSR 1287 29 3 10 Scratch Pad Register SCR 1288 29 3 11 Divisor Latches DLL and DLH 1288 29 3 12 Revision Identification Registers REVID1 and REVID2 1290 29 3 13 Power and Emulation Management Register PWREMU_MGMT 1291 29 3 14 Mode Definition Register MDR 1292 30 Universal Serial Bus OHCI Host Controller 1293 30 1 Introduction 1294 3...

Page 18: ... Architecture 1321 31 2 1 Clock Control 1321 31 2 2 Signal Descriptions 1323 31 2 3 Indexed and Non Indexed Registers 1323 31 2 4 USB PHY Initialization 1324 31 2 5 VBUS Voltage Sourcing Control 1324 31 2 6 Dynamic FIFO Sizing 1324 31 2 7 USB Controller Host and Peripheral Modes Operation 1325 31 2 8 Communications Port Programming Interface CPPI 4 1 DMA Overview 1361 31 2 9 Test Modes 1385 31 2 1...

Page 19: ...ransmit Endpoint PERI_TXCSR 1433 31 4 36 Control Status Register for Host Transmit Endpoint HOST_TXCSR 1434 31 4 37 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP 1435 31 4 38 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR 1436 31 4 39 Control Status Register for Host Receive Endpoint HOST_RXCSR 1437 31 4 40 Count 0 Register COUNT0 1438 31 4 41 Receive Count Re...

Page 20: ...Manager Free Descriptor Buffer Starvation Count Register 0 FDBSC0 1460 31 4 78 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 1461 31 4 79 Queue Manager Free Descriptor Buffer Starvation Count Register 2 FDBSC2 1462 31 4 80 Queue Manager Free Descriptor Buffer Starvation Count Register 3 FDBSC3 1463 31 4 81 Queue Manager Linking RAM Region 0 Base Address Register LRAM0BASE...

Page 21: ...Register PROGn_MPPA 99 5 17 Fault Address Register FLTADDRR 100 5 18 Fault Status Register FLTSTAT 101 5 19 Fault Clear Register FLTCLR 102 6 1 Overall Clocking Diagram 105 6 2 USB Clocking Diagram 107 6 3 EMIFB Clocking Diagram 110 6 4 EMIFA Clocking Diagram 111 6 5 EMAC Clocking Diagram 112 7 1 PLL0 Structure 117 7 2 Revision Identification Register REVID 122 7 3 Reset Type Status Register RSTYP...

Page 22: ...gister MDSTATn 161 8 18 PSC0 Module Control n Register MDCTLn 162 8 19 PSC1 Module Control n Register MDCTLn 163 10 1 Revision Identification Register REVID 177 10 2 Device Identification Register 0 DEVIDR0 177 10 3 Boot Configuration Register BOOTCFG 178 10 4 Silicon Revision Identification Register CHIPREVID 178 10 5 Kick 0 Register KICK0R 179 10 6 Kick 1 Register KICK1R 179 10 7 Host 1 Configur...

Page 23: ...Capture and APWM Modes of Operation 246 13 3 Capture Function Diagram 247 13 4 Event Prescale Control 248 13 5 Prescale Function Waveforms 248 13 6 Continuous One shot Block Diagram 249 13 7 Counter and Synchronization Block Diagram 250 13 8 Interrupts in eCAP Module 252 13 9 PWM Waveform Details Of APWM Mode Operation 253 13 10 Capture Sequence for Absolute Time Stamp Rising Edge Detect 255 13 11...

Page 24: ...metric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High 312 14 23 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 314 14 24 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 316 14 25 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 318 14 26 Up...

Page 25: ...ge Stage FPWM2 FPWM1 368 14 64 ZVS Full H Bridge Waveforms 369 14 65 Time Base Control Register TBCTL 371 14 66 Time Base Status Register TBSTS 373 14 67 Time Base Phase Register TBPHS 374 14 68 Time Base Counter Register TBCNT 374 14 69 Time Base Period Register TBPRD 375 14 70 Counter Compare Control Register CMPCTL 376 14 71 Counter Compare A Register CMPA 377 14 72 Counter Compare B Register C...

Page 26: ...ration 417 15 21 eQEP Position Counter Register QPOSCNT 419 15 22 eQEP Position Counter Initialization Register QPOSINIT 419 15 23 eQEP Maximum Position Count Register QPOSMAX 419 15 24 eQEP Position Compare Register QPOSCMP 420 15 25 eQEP Index Position Latch Register QPOSILAT 420 15 26 eQEP Strobe Position Latch Register QPOSSLAT 420 15 27 eQEP Position Counter Latch Register QPOSLAT 421 15 28 e...

Page 27: ... PaRAM 492 16 27 Servicing Continuous McBSP Data Example Reload PaRAM 492 16 28 Ping Pong Buffering for McBSP Data Example 495 16 29 Ping Pong Buffering for McBSP Example PaRAM 496 16 30 Ping Pong Buffering for McBSP Example Pong PaRAM 496 16 31 Ping Pong Buffering for McBSP Example Ping PaRAM 497 16 32 Intermediate Transfer Completion Chaining Example 499 16 33 Single Large Block Transfer Example...

Page 28: ...r IEVAL 540 16 76 QDMA Event Register QER 541 16 77 QDMA Event Enable Register QEER 542 16 78 QDMA Event Enable Clear Register QEECR 543 16 79 QDMA Event Enable Set Register QEESR 543 16 80 QDMA Secondary Event Register QSER 544 16 81 QDMA Secondary Event Clear Register QSECR 545 16 82 Revision ID Register REVID 547 16 83 EDMA3TC Configuration Register TCCFG 548 16 84 EDMA3TC Channel Status Regist...

Page 29: ...mit Interrupt Enable Register CnTXEN 623 17 18 EMAC Control Module Interrupt Core 0 2 Miscellaneous Interrupt Enable Register CnMISCEN 624 17 19 EMAC Control Module Interrupt Core 0 2 Receive Threshold Interrupt Status Register CnRXTHRESHSTAT 625 17 20 EMAC Control Module Interrupt Core 0 2 Receive Interrupt Status Register CnRXSTAT 626 17 21 EMAC Control Module Interrupt Core 0 2 Transmit Interru...

Page 30: ...Receive Unicast Clear Register RXUNICASTCLEAR 667 17 62 Receive Maximum Length Register RXMAXLEN 668 17 63 Receive Buffer Offset Register RXBUFFEROFFSET 668 17 64 Receive Filter Low Priority Frame Threshold Register RXFILTERLOWTHRESH 669 17 65 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH 669 17 66 Receive Channel n Free Buffer Count Register RXnFREEBUFFER 670 17 67 MAC Control R...

Page 31: ...veform of an ASRAM Read 742 18 24 Timing Waveform of an ASRAM Write 743 18 25 Timing Waveform of an ASRAM Read with PCB Delays 745 18 26 Timing Waveform of an ASRAM Write with PCB Delays 746 18 27 Timing Waveform of a NAND Flash Read 751 18 28 Timing Waveform of a NAND Flash Command Write 753 18 29 Timing Waveform of a NAND Flash Address Write 753 18 30 Timing Waveform of a NAND Flash Data Write 7...

Page 32: ...ister SDCFG2 815 19 19 Peripheral Bus Burst Priority Register BPRIO 816 19 20 Performance Counter 1 Register PC1 817 19 21 Performance Counter 2 Register PC2 817 19 22 Performance Counter Configuration Register PCC 818 19 23 Performance Counter Master Region Select Register PCMRS 820 19 24 Performance Counter Time Register PCT 821 19 25 Interrupt Raw Register IRR 821 19 26 Interrupt Mask Register ...

Page 33: ... 4 and 5 Set Rise Trigger Register SET_FAL_TRIG45 851 20 42 GPIO Banks 6 and 7 Set Rise Trigger Register SET_FAL_TRIG67 851 20 43 GPIO Bank 8 Set Rise Trigger Register SET_FAL_TRIG8 852 20 44 GPIO Banks 0 and 1 Clear Rise Trigger Register CLR_FAL_TRIG01 853 20 45 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_FAL_TRIG23 853 20 46 GPIO Banks 4 and 5 Clear Rise Trigger Register CLR_FAL_TRIG45 85...

Page 34: ...ing Arbitration 895 22 5 Bit Transfer on the I2C Bus 896 22 6 I2C Peripheral START and STOP Conditions 896 22 7 I2C Peripheral Data Transfer 897 22 8 I2C Peripheral 7 Bit Addressing Format FDF 0 XA 0 in ICMDR 897 22 9 I2C Peripheral 10 Bit Addressing Format With Master Transmitter Writing to Slave Receiver FDF 0 XA 1 in ICMDR 898 22 10 I2C Peripheral Free Data Format FDF 1 in ICMDR 898 22 11 I2C P...

Page 35: ...ration Register LIDD_CSn_CONF 957 23 20 LCD LIDD CSn Address Read Write Register LIDD_CSn_ADDR 958 23 21 LCD LIDD CSn Data Read Write Register LIDD_CSn_DATA 959 23 22 LCD Raster Control Register RASTER_CTRL 960 23 23 Monochrome Passive Mode Pixel Clock and Data Pin Timing 963 23 24 Color Passive Mode Pixel Clock and Data Pin Timing 963 23 25 Active Mode Pixel Clock and Data Pin Timing 964 23 26 TF...

Page 36: ...SP Service Time Upon Transmit DMA Event AXEVT 1017 24 26 DSP Service Time Upon Receive DMA Event AREVT 1018 24 27 DMA Events in an Audio Example Two Events 1020 24 28 McASP Audio FIFO AFIFO Block Diagram 1021 24 29 Data Flow Through Transmit Format Unit 1024 24 30 Data Flow Through Receive Format Unit 1026 24 31 Audio Mute AMUTE Block Diagram 1028 24 32 Transmit Clock Failure Detection Circuit Blo...

Page 37: ...Right Channel Status Registers DITCSRB0 DITCSRB5 1086 24 73 DIT Left Channel User Data Registers DITUDRA0 DITUDRA5 1087 24 74 DIT Right Channel User Data Registers DITUDRB0 DITUDRB5 1087 24 75 Transmit Buffer Registers XBUFn 1088 24 76 Receive Buffer Registers RBUFn 1088 24 77 AFIFO Revision Identification Register AFIFOREV 1089 24 78 Write FIFO Control Register WFIFOCTL 1090 24 79 Write FIFO Stat...

Page 38: ...38 SDIO Control Register SDIOCTL 1143 25 39 SDIO Status Register 0 SDIOST0 1144 25 40 SDIO Interrupt Enable Register SDIOIEN 1145 25 41 SDIO Interrupt Status Register SDIOIST 1145 25 42 MMC FIFO Control Register MMCFIFOCTL 1146 26 1 Real Time Clock Block Diagram 1148 26 2 32 kHz Oscillator Counter Compensation 1152 26 3 Kick State Machine 1153 26 4 Second Register SECOND 1156 26 5 Minute Register ...

Page 39: ...1206 27 23 SPI Pin Control Register 0 SPIPC0 1208 27 24 SPI Pin Control Register 1 SPIPC1 1209 27 25 SPI Pin Control Register 2 SPIPC2 1210 27 26 SPI Pin Control Register 3 SPIPC3 1211 27 27 SPI Pin Control Register 4 SPIPC4 1212 27 28 SPI Pin Control Register 5 SPIPC5 1213 27 29 SPI Data Register 0 SPIDAT0 1214 27 30 SPI Data Register 1 SPIDAT1 1215 27 31 SPI Buffer Register SPIBUF 1216 27 32 SPI...

Page 40: ...264 29 4 UART Protocol Formats 1266 29 5 UART Interface Using Autoflow Diagram 1269 29 6 Autoflow Functional Timing Waveforms for UARTn_RTS 1270 29 7 Autoflow Functional Timing Waveforms for UARTn_CTS 1270 29 8 UART Interrupt Request Enable Paths 1272 29 9 Receiver Buffer Register RBR 1275 29 10 Transmitter Holding Register THR 1276 29 11 Interrupt Enable Register IER 1277 29 12 Interrupt Identifi...

Page 41: ... Service Routine Flow Chart 1326 31 4 CPU Actions at Transfer Phases 1331 31 5 Sequence of Transfer 1331 31 6 Service Endpoint 0 Flow Chart 1333 31 7 IDLE Mode Flow Chart 1334 31 8 TX Mode Flow Chart 1335 31 9 RX Mode Flow Chart 1336 31 10 Setup Phase of a Control Transaction Flow Chart 1346 31 11 IN Data Phase Flow Chart 1348 31 12 OUT Data Phase Flow Chart 1350 31 13 Completion of SETUP or OUT D...

Page 42: ...Status and Control Registers INDEX 1429 31 57 Register to Enable the USB 2 0 Test Modes TESTMODE 1429 31 58 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP 1430 31 59 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSR0 1431 31 60 Control Status Register for Endpoint 0 in Host Mode HOST_CSR0 1432 31 61 Control Status Register for Peripheral Transmit Endpoint PERI_TX...

Page 43: ...duler Control Register DMA_SCHED_CTRL 1457 31 100 CDMA Scheduler Table Word n Registers WORD n 1457 31 101 Queue Manager Revision Identification Register QMGRREVID 1459 31 102 Queue Manager Queue Diversion Register DIVERSION 1459 31 103 Queue Manager Free Descriptor Buffer Starvation Count Register 0 FDBSC0 1460 31 104 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 1461 31...

Page 44: ...gister PROGn_MPEAR Field Descriptions 98 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions 99 5 20 Fault Address Register FLTADDRR Field Descriptions 100 5 21 Fault Status Register FLTSTAT Field Descriptions 101 5 22 Fault Clear Register FLTCLR Field Descriptions 102 6 1 Device Clock Inputs 104 6 2 System Clock Domains 104 6 3 Example PLL Frequencies ...

Page 45: ...ror Pending Register PERRPR Field Descriptions 152 8 13 Power Error Clear Register PERRCR Field Descriptions 152 8 14 Power Domain Transition Command Register PTCMD Field Descriptions 153 8 15 Power Domain Transition Status Register PTSTAT Field Descriptions 154 8 16 Power Domain 0 Status Register PDSTAT0 Field Descriptions 155 8 17 Power Domain 1 Status Register PDSTAT1 Field Descriptions 156 8 1...

Page 46: ...ster PINMUX14 Field Descriptions 215 10 37 Pin Multiplexing Control 15 Register PINMUX15 Field Descriptions 217 10 38 Pin Multiplexing Control 16 Register PINMUX16 Field Descriptions 219 10 39 Pin Multiplexing Control 17 Register PINMUX17 Field Descriptions 221 10 40 Pin Multiplexing Control 18 Register PINMUX18 Field Descriptions 223 10 41 Pin Multiplexing Control 19 Register PINMUX19 Field Descr...

Page 47: ...14 6 Counter Compare Submodule Key Signals 302 14 7 Action Qualifier Submodule Registers 306 14 8 Action Qualifier Submodule Possible Input Events 307 14 9 Action Qualifier Event Priority for Up Down Count Mode 309 14 10 Action Qualifier Event Priority for Up Count Mode 309 14 11 Action Qualifier Event Priority for Down Count Mode 309 14 12 Behavior if CMPA CMPB is Greater than the Period 310 14 1...

Page 48: ...Descriptions 379 14 63 Action Qualifier Output B Control Register AQCTLB Field Descriptions 380 14 64 Action Qualifier Software Force Register AQSFRC Field Descriptions 381 14 65 Action Qualifier Continuous Software Force Register AQCSFRC Field Descriptions 382 14 66 Dead Band Generator Submodule Registers 382 14 67 Dead Band Generator Control Register DBCTL Field Descriptions 383 14 68 Dead Band ...

Page 49: ...Field Descriptions 429 15 20 eQEP Interrupt Clear Register QCLR Field Descriptions 430 15 21 eQEP Interrupt Force Register QFRC Field Descriptions 432 15 22 eQEP Status Register QEPSTS Field Descriptions 433 15 23 eQEP Capture Time Register QCTMR Field Descriptions 434 15 24 eQEP Capture Period Register QCPRD Field Descriptions 434 15 25 eQEP Capture Timer Latch Register QCTMRLAT Field Description...

Page 50: ...ter ESR Field Descriptions 531 16 43 Chained Event Register CER Field Descriptions 532 16 44 Event Enable Register EER Field Descriptions 533 16 45 Event Enable Clear Register EECR Field Descriptions 534 16 46 Event Enable Set Register EESR Field Descriptions 534 16 47 Secondary Event Register SER Field Descriptions 535 16 48 Secondary Event Clear Register SECR Field Descriptions 535 16 49 Interru...

Page 51: ...MDIO Signals for MII Interface 576 17 2 EMAC and MDIO Signals for RMII Interface 577 17 3 Ethernet Frame Description 578 17 4 Basic Descriptor Description 580 17 5 Receive Frame Treatment Summary 605 17 6 Middle of Frame Overrun Treatment 606 17 7 Emulation Control 616 17 8 EMAC Control Module Registers 617 17 9 EMAC Control Module Revision ID Register REVID Field Descriptions 618 17 10 EMAC Contr...

Page 52: ...ECTOR Field Descriptions 656 17 50 Receive Interrupt Status Unmasked Register RXINTSTATRAW Field Descriptions 657 17 51 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions 658 17 52 Receive Interrupt Mask Set Register RXINTMASKSET Field Descriptions 659 17 53 Receive Interrupt Mask Clear Register RXINTMASKCLEAR Field Descriptions 660 17 54 MAC Interrupt Status Unmasked Regi...

Page 53: ...ming Register SDSRETR 702 18 11 SDRAM LOAD MODE REGISTER Command 703 18 12 Refresh Urgency Levels 704 18 13 Mapping from Logical Address to EMIFA Pins for 16 bit SDRAM 709 18 14 Normal Mode vs Select Strobe Mode 710 18 15 Description of the Asynchronous m Configuration Register CEnCFG 712 18 16 Description of the Asynchronous Wait Cycle Configuration Register AWCC 713 18 17 Description of the EMIF...

Page 54: ...R Field Descriptions 774 18 62 NAND Flash n ECC Register NANDFnECC Field Descriptions 775 18 63 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD Field Descriptions 776 18 64 NAND Flash 4 Bit ECC Register 1 NAND4BITECC1 Field Descriptions 777 18 65 NAND Flash 4 Bit ECC Register 2 NAND4BITECC2 Field Descriptions 777 18 66 NAND Flash 4 Bit ECC Register 3 NAND4BITECC3 Field Descriptions 778 18 67 NA...

Page 55: ...Mask Clear Register IMCR Field Descriptions 823 20 1 GPIO Register Bits and Banks Associated With GPIO Signals 827 20 2 GPIO Registers 834 20 3 Revision ID Register REVID Field Descriptions 835 20 4 GPIO Interrupt Per Bank Enable Register BINTEN Field Descriptions 836 20 5 GPIO Direction Register DIRn Field Descriptions 838 20 6 GPIO Output Data Register OUT_DATAn Field Descriptions 840 20 7 GPIO ...

Page 56: ...rrupt Vector Register ICIVR Field Descriptions 920 22 18 I2C Extended Mode Register ICEMDR Field Descriptions 921 22 19 I2C Prescaler Register ICPSC Field Descriptions 922 22 20 I2C Revision Identification Register 1 REVID1 Field Descriptions 923 22 21 I2C Revision Identification Register 2 REVID2 Field Descriptions 923 22 22 I2C DMA Control Register ICDMAC Field Descriptions 924 22 23 I2C Pin Fun...

Page 57: ... 1046 24 14 Pin Data Input Register PDIN Field Descriptions 1048 24 15 Pin Data Set Register PDSET Field Descriptions 1050 24 16 Pin Data Clear Register PDCLR Field Descriptions 1052 24 17 Global Control Register GBLCTL Field Descriptions 1053 24 18 Audio Mute Control Register AMUTE Field Descriptions 1055 24 19 Digital Loopback Control Register DLBCTL Field Descriptions 1057 24 20 Digital Mode Co...

Page 58: ... Interrupt Mask Register MMCIM Field Descriptions 1130 25 11 MMC Response Time Out Register MMCTOR Field Descriptions 1132 25 12 MMC Data Read Time Out Register MMCTOD Field Descriptions 1133 25 13 MMC Block Length Register MMCBLEN Field Descriptions 1134 25 14 MMC Number of Blocks Register MMCNBLK Field Descriptions 1135 25 15 MMC Number of Blocks Counter Register MMCNBLC Field Descriptions 1135 ...

Page 59: ...IGCR0 Field Descriptions 1200 27 10 SPI Global Control Register 1 SPIGCR1 Field Descriptions 1201 27 11 SPI Interrupt Register SPIINT0 Field Descriptions 1203 27 12 SPI Interrupt Level Register SPILVL Field Descriptions 1205 27 13 SPI Flag Register SPIFLG Field Descriptions 1206 27 14 SPI Pin Control Register 0 SPIPC0 Field Descriptions 1208 27 15 SPI Pin Control Register 1 SPIPC1 Field Descriptio...

Page 60: ... 5 UART Interrupt Requests Descriptions 1272 29 6 UART Registers 1274 29 7 Receiver Buffer Register RBR Field Descriptions 1275 29 8 Transmitter Holding Register THR Field Descriptions 1276 29 9 Interrupt Enable Register IER Field Descriptions 1277 29 10 Interrupt Identification Register IIR Field Descriptions 1278 29 11 Interrupt Identification and Interrupt Clearing Information 1279 29 12 FIFO C...

Page 61: ... 2 PHY PLL Clock Frequencies Supported 1322 31 3 USB Terminal Functions 1323 31 4 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions 1338 31 5 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions 1339 31 6 PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions 1341 31 7 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions 1343 31 8 Host Packe...

Page 62: ... USB Interrupts INTRUSB Field Descriptions 1427 31 58 Interrupt Enable Register for INTRUSB INTRUSBE Field Descriptions 1428 31 59 Frame Number Register FRAME Field Descriptions 1428 31 60 Index Register for Selecting the Endpoint Status and Control Registers INDEX Field Descriptions 1429 31 61 Register to Enable the USB 2 0 Test Modes TESTMODE Field Descriptions 1429 31 62 Maximum Packet Size for...

Page 63: ... Descriptions 1455 31 102 Receive Channel n Host Packet Configuration Registers B RXHPCRB n Field Descriptions 1456 31 103 CDMA Scheduler Control Register DMA_SCHED_CTRL Field Descriptions 1457 31 104 CDMA Scheduler Table Word n Registers WORD n Field Descriptions 1457 31 105 Queue Manager Revision Identification Register QMGRREVID Field Descriptions 1459 31 106 Queue Manager Queue Diversion Regis...

Page 64: ...nt documentation that describes related peripherals and other technical collateral is available in the C6000 DSP product folder at www ti com c6000 SPRUFK5 TMS320C674x DSP Megamodule Reference Guide Describes the TMS320C674x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory...

Page 65: ...arch 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Overview Chapter 1 SPRUH91D March 2013 Revised September 2016 Overview Topic Page 1 1 Introduction 66 ...

Page 66: ...rview 1 1 Introduction The C6745 C6747 DSP efficiently handles communication and audio processing tasks The C6745 C6747 DSP consists of the following primary components DSP subsystem and associated memories A set of I O peripherals A powerful DMA subsystem and SDRAM EMIF interface Block Diagram A block diagram for the C6745 DSP is shown in TMS320C6745 DSP Block Diagram A block diagram for the C674...

Page 67: ...Ctlr PHY USB2 0 OTG Ctlr PHY HPI MMC SD 8b EMIFA 8b 16B NAND Flash 16b SDRAM EMIFB SDRAM Only 16b 32b GPIO PRU Subsystem System Control Input Clock s Power Sleep Controller Memory Protection Pin Multiplexing RTC 32 kHz OSC PLL Clock Generator w OSC General Purpose Timer General Purpose Timer Watchdog www ti com Introduction 67 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedbac...

Page 68: ...ation Feedback Copyright 2013 2016 Texas Instruments Incorporated DSP Subsystem Chapter 2 SPRUH91D March 2013 Revised September 2016 DSP Subsystem Topic Page 2 1 Introduction 69 2 2 TMS320C674x Megamodule 70 2 3 Memory Map 74 2 4 Advanced Event Triggering AET 75 ...

Page 69: ...Introduction 69 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated DSP Subsystem 2 1 Introduction The DSP subsystem Figure 2 1 includes TI s standard TMS320C674x megamodule and several blocks of internal memory L1P L1D and L2 This document provides an overview of the DSP subsystem and the following considerations associated w...

Page 70: ...and L2 cache for caching external memory locations The internal direct memory access controller IDMA manages DMA among the L1P L1D and L2 memories For more information about each of these controllers see the TMS320C674x DSP Megamodule Reference Guide SPRUFK5 2 2 2 Internal Peripherals The C674x megamodule includes the following internal peripherals DSP interrupt controller INTC DSP power down cont...

Page 71: ...oller Interrupt 21 USB1_R WAKEUP 1 USB1 USB1 1 Remote Wakeup Interrupt 22 Reserved 23 EHRPWM1TZ HiResTimer PWM1 Trip Zone Interrupt 24 EHRPWM2 HiResTimer PWM2 Interrupt 25 EHRPWM2TZ HiResTimer PWM2 Trip Zone Interrupt 26 EMAC_C0RXTHRESH EMAC Core 0 Receive Threshold Interrupt 27 EMAC_C0RX EMAC Core 0 Receive Interrupt 28 EMAC_C0TX EMAC Core 0 Transmit Interrupt 29 EMAC_C0MISC EMAC Core 0 Miscellan...

Page 72: ...YSCFG_CHIPINT3 SYSCFG CHIPSIG Register 68 EQEP0 EQEP0 69 UART2_INT UART2 70 PSC0_ALLINT PSC0 71 PSC1_ALLINT PSC1 72 GPIO_B7INT GPIO Bank 7 Interrupt 73 LCDC_INT 2 LCD Controller 74 MPU_BOOTCFG_ERR MPU Shared Interrupt 75 77 Reserved 78 T64P0_CMPINT0 Timer64P0 Compare 0 79 T64P0_CMPINT1 Timer64P0 Compare 1 80 T64P0_CMPINT2 Timer64P0 Compare 2 81 T64P0_CMPINT3 Timer64P0 Compare 3 82 T64P0_CMPINT4 Ti...

Page 73: ...signal register CHIPSIG and the chip signal clear register CHIPSIG_CLR The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG The NMI interrupt is cleared by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR For more information on the System Configuration Module CHIPSIG and CHIPSIG_CLR see the System Configuration SYSCFG Module chapter 2 2 2 2 Power Down Controller PDC The C674x...

Page 74: ... assigned a priority level on a per transfer basis The programmable priority level has a single meaning throughout the system There are a total of nine priority levels where priority zero is the highest priority and priority eight is the lowest priority When requests for a single resource contend access is granted to the highest priority requestor When the contention occurs for multiple successive...

Page 75: ...applications AET provides the following capabilities Hardware Program Breakpoints specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture Data Watchpoints specify data variable addresses address ranges or data values that can generate events such as halting the processor or triggering the trace capture Counters count the occurrence...

Page 76: ... Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated System Interconnect Chapter 3 SPRUH91D March 2013 Revised September 2016 System Interconnect Topic Page 3 1 Introduction 77 3 2 System Interconnect Block Diagram 78 ...

Page 77: ...pically capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to and from them The system master peripherals include the DSP the EDMA3 transfer controllers EMAC HPI LCDC and USB Not all master peripherals may connect to all slave peripherals The supported connections are designated by an X in Table 3 1 1 EDMA3TC group EDMA3TC0 ED...

Page 78: ...P2 SCR10 eHRPWM0 eHRPWM1 eHRPWM2 eCAP0 eCAP1 eCAP2 eQEP0 eQEP1 EDMA3 CC EDMA3 CC Legend 32 Bit BUS 64 Bit BUS IP Module Synchronous Bridge Asynchronous Bridge SCR Paths with dashed lines cross the subchip boundary BR9 BR10 BR11 BR12 EMAC USB1 SCR8 BR13 BR14 BR15 A A A A A A A A rd 128k Shared RAM A MPU2 PRU0 PRU1 PRU Cfg System Interconnect Block Diagram www ti com 78 SPRUH91D March 2013 Revised S...

Page 79: ...er 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated System Memory Chapter 4 SPRUH91D March 2013 Revised September 2016 System Memory Topic Page 4 1 Introduction 80 4 2 DSP Memories 80 4 3 Peripherals 81 ...

Page 80: ...ou to configure part of the L1D RAM as normal data RAM or as cache You can configure cache sizes of 0 kB 4 kB 8 kB 16 kB or 32 kB of the 32 kB of RAM The default configuration is 32 kB cache L2 memory includes 256 kB of RAM The DSP unified memory controller UMC allows you to configure part or all of the L2 RAM as normal RAM or as cache You can configure cache sizes of 0 kB 4 kB 8 kB 16 kB 32 kB 64...

Page 81: ...2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated System Memory 4 3 Peripherals The DSP has access to all peripherals on the device See the device specific data manual for the complete list of peripherals supported on your device ...

Page 82: ... Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Memory Protection Unit MPU Chapter 5 SPRUH91D March 2013 Revised September 2016 Memory Protection Unit MPU Topic Page 5 1 Introduction 83 5 2 Architecture 84 5 3 MPU Registers 89 ...

Page 83: ...grammable address ranges Supports 0 or 1 fixed range Supports read write and execute access privileges Supports privilege ID associations with ranges Generates an interrupt when there is a protection violation and saves violating transfer parameters Supports L1 L2 cache accesses Supports protection of its own registers 5 1 3 Block Diagram Figure 5 1 shows a block diagram of the MPU An access to a ...

Page 84: ... Levels The privilege level of a memory access determines what level of permissions the originator of the memory access might have Two privilege levels are supported supervisor and user Supervisor level is generally granted access to peripheral registers and the memory protection configuration User level is generally confined to the memory spaces that the OS specifically designates for its use DSP...

Page 85: ...ted memory One of the programmable address ranges could be used to detect accesses to this unpopulated memory The MPU divides its assigned memory into address ranges Each MPU can support one fixed address range and multiple programmable address ranges The fixed address range is configured to an exact address The programmable address range allows software to program the start and end addresses Each...

Page 86: ...emory protection page attribute registers MPPA AID0 through AID11 are used to specify the allowed privilege IDs An additional allowed ID bit AIDX captures access made by all privilege IDs not covered by AID0 through AID11 When set to 1 the AID bit grants access to the corresponding ID When cleared to 0 the AID bit denies access to the corresponding requestor 5 2 3 2 Request Type Based Permissions ...

Page 87: ...west of each type of permission from any hit range Therefore if a transfer matches 2 ranges one that is RW and one that is RX then the final permission is just R The MPU has a special mechanism for handling DSP L1 L2 cache controller read accesses see Section 5 2 5 for more details 5 2 5 DSP L1 L2 Cache Controller Accesses A memory read access that originates from the DSP L1 L2 cache is treated di...

Page 88: ...set Considerations After reset the memory protection page attribute registers MPPA default to 0 This disables all protection features 5 2 9 Interrupt Support 5 2 9 1 Interrupt Events and Requests The MPU generates two interrupts an address error interrupt MPU_ADDR_ERR_INT and a protection interrupt MPU_PROT_ERR_INT The MPU_ADDR_ERR_INT is generated when there is an addressing violation due to an a...

Page 89: ...01E1 4228h PROG3_MPPA Programmable range 3 memory protection page attributes register Section 5 3 12 01E1 4230h PROG4_MPSAR Programmable range 4 start address register Section 5 3 10 1 01E1 4234h PROG4_MPEAR Programmable range 4 end address register Section 5 3 11 1 01E1 4238h PROG4_MPPA Programmable range 4 memory protection page attributes register Section 5 3 12 01E1 4240h PROG5_MPSAR Programma...

Page 90: ...le range 6 end address register Section 5 3 11 2 01E1 5258h PROG6_MPPA Programmable range 6 memory protection page attributes register Section 5 3 12 01E1 5260h PROG7_MPSAR Programmable range 7 start address register Section 5 3 10 2 01E1 5274h PROG7_MPEAR Programmable range 7 end address register Section 5 3 11 2 01E1 5268h PROG7_MPPA Programmable range 7 memory protection page attributes registe...

Page 91: ...IDs may be supported on your device Unsupported AIDs should be cleared to 0 in the memory page protection attributes registers MPPA See Table 5 3 for a list of AIDs supported on your device 1 For MPU1 2 For MPU2 Figure 5 4 Configuration Register CONFIG 31 24 23 20 19 16 ADDR_WIDTH NUM_FIXED NUM_PROG R 0 1 or 6h 2 R 0 1 or 1 2 R 6h 1 or Ch 2 15 12 11 1 0 NUM_AIDS Reserved ASSUME_ALLOWED R Ch R 0 R ...

Page 92: ...RAWSTAT is shown in Figure 5 5 and described in Table 5 10 Figure 5 5 Interrupt Raw Status Set Register IRAWSTAT 31 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 10 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error Read...

Page 93: ...re 5 6 Interrupt Enable Status Clear Register IENSTAT 31 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 11 Interrupt Enable Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error If the interrupt is enabled reading this bit reflects the s...

Page 94: ...ss violation error enable 0 Writing 0 has no effect 1 Interrupt is enabled 0 PROTERR_EN Protection violation error enable 0 Writing 0 has no effect 1 Interrupt is enabled 5 3 6 Interrupt Enable Clear Register IENCLR Reading the interrupt enable clear register IENCLR returns the interrupts that are enabled Software can write to IENCLR to clear disable an interrupt Writes of 0 have no effect The IEN...

Page 95: ...register FXD_MPEAR which instead read as 0 The FXD_MPSAR is shown in Figure 5 9 Figure 5 9 Fixed Range Start Address Register FXD_MPSAR 31 0 Reserved R 0 LEGEND R Read only n value after reset 5 3 8 Fixed Range End Address Register FXD_MPEAR The fixed range end address register FXD_MPEAR holds the end address for the fixed range The fixed address range manages access to the EMIFB control registers...

Page 96: ...R W 1 R W 1 R W 1 R W 1 R W 1 R 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 5 14 Fixed Range Memory Protection Page Attributes Register FXD_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is granted 9 AIDX Contro...

Page 97: ... width of the address field in PROGn_MPSAR and the programmable range n end address register PROGn_MPEAR For example to protect a 64 kB page starting at byte address 8001 0000h write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR 5 3 10 1 MPU1 Programmable Range n Start Address Register PROG1_MPSAR PROG6_MPSAR The PROGn_MPSAR for MPU1 is shown in Figure 5 12 and described in Table 5 15 Fi...

Page 98: ...Programmable Range n End Address Register PROG1_MPEAR PROG6_MPEAR The PROGn_MPEAR for MPU1 is shown in Figure 5 14 and described in Table 5 17 Figure 5 14 MPU1 Programmable Range n End Address Register PROGn_MPEAR 31 10 9 0 END_ADDR Reserved R W 20 007Fh R 3FFh LEGEND R W Read Write R Read only n value after reset Table 5 17 MPU1 Programmable Range n End Address Register PROGn_MPEAR Field Descript...

Page 99: ...W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is gr...

Page 100: ...er FLTADDRR The fault address register FLTADDRR holds the address of the first protection fault transfer The FLTADDRR is shown in Figure 5 17 and described in Table 5 20 Figure 5 17 Fault Address Register FLTADDRR 31 0 FLTADDR R 0 LEGEND R Read only n value after reset Table 5 20 Fault Address Register FLTADDRR Field Descriptions Bit Field Value Description 31 0 FLTADDR 0 FFFF FFFFh Memory address...

Page 101: ...END R Read only n value after reset Table 5 21 Fault Status Register FLTSTAT Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 MSTID 0 FFh Master ID of fault transfer 15 13 Reserved 0 Reserved 12 9 PRIVID 0 Fh Privilege ID of fault transfer 8 6 Reserved 0 Reserved 5 0 TYPE 0 3Fh Fault type The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault ...

Page 102: ...ster FLTSTAT as well as produce an interrupt Only the TYPE bit field in FLTSTAT is cleared when a 1 is written to the CLEAR bit The FLTCLR is shown in Figure 5 19 and described in Table 5 22 Figure 5 19 Fault Clear Register FLTCLR 31 16 Reserved R 0 15 1 0 Reserved CLEAR R 0 W 0 LEGEND R Read only W Write only n value after reset Table 5 22 Fault Clear Register FLTCLR Field Descriptions Bit Field ...

Page 103: ...ubmit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Device Clocking Chapter 6 SPRUH91D March 2013 Revised September 2016 Device Clocking Topic Page 6 1 Overview 104 6 2 Frequency Flexibility 105 6 3 Peripheral Clocking 107 ...

Page 104: ...ee system clock domains that do not require a fixed ratio to the CPU clock frequency these are SYSCLK3 SYSCLK5 and SYSCLK7 Figure 6 1 shows the clocking architecture 1 This peripheral is not supported on the C6745 DSP 2 McASP2 is not supported on the C6745 DSP only McASP0 and McASP1 are supported on the C6745 DSP Table 6 1 Device Clock Inputs Peripheral Input Clock Signal Name Oscillator PLL OSCIN...

Page 105: ...power savings mode PLL Active where the PLL is enabled and multiplies the input clock up to the desired operating frequency When the PLL is in Bypass mode the reference clock supplied on OSCIN serves as the clock source from which all of the system clocks SYSCLK1 SYSCLK7 are derived This means when the PLL is in Bypass mode the reference clock supplied on OSCIN passes directly to the system of PLL...

Page 106: ...d by the value programmed in the RATIO field of the PLL post divider control register POSTDIV For Div1 Div2 Div3 and Div4 modes the RATIO field would be programmed to 0 1 2 and 3 respectively The Div1 Div2 Div3 and Div4 modes are shown here as an example Additional post divider modes are supported and are documented in the Phase Locked Loop Controller PLLC chapter NOTE PLL power consumption increa...

Page 107: ...s to the USB2 0 subsystem The USB2 0 subsystem peripheral bus clock is sourced from SYSCLK2 The USB1 1 subsystem requires both a 48 MHz CLK48 and a 12 MHz CLK12 clock input The 12 MHz clock is derived from the 48 MHz clock The 48 MHz clock required by the USB1 1 subsystem can be sourced from either the USB_REFCLKIN or from the 48 MHz clock provided by the USB2 0 PHY The CLK48 source is selected by...

Page 108: ... PLL inside the USB2 0 PHY can be configured to accept any of these input clock frequencies 0 1 USB_REFCLKIN USB_REFCLKIN USB_REFCLKIN must be 48 MHz The PLL inside the USB2 0 PHY can be configured to accept this input clock frequency 1 0 PLL0_AUXCLK CLK48MHZ output from USB2 0 PHY PLL0_AUXCLK must be 12 24 48 19 2 38 4 13 26 20 or 40 MHz The PLL inside the USB2 0 PHY can be configured to accept a...

Page 109: ...e divider ratio for SYSCLK5 can be changed to achieve various clock frequencies For certain PLL multiplier and PLL post divider control register POSTDIV settings a higher clock frequency can be achieved by selecting SYSCLK5 as the clock source for MCLK As shown in Figure 6 3 the EMIFB output clock EMB_CLK can be sourced from either the output of the EMIFB LPSC CLK1 in Figure 6 3 or directly from t...

Page 110: ... for an explanation of POSTDIV divider modes Table 6 5 EMIFB MCLK Frequencies OSCIN Frequency PLL Multiplier Register Setting Multiplier Frequency MHz Post Divider Mode 1 POSTDIV Output Frequency DIV4P5 PLLDIV5 Register Setting SYSCLK5 25 24 600 Div2 300 MHz 133 MHz 2 100 MHz Div3 200 MHz 133 MHz 2 66 6 MHz 1 100 MHz Div4 150 MHz 133 MHz 1 75 MHz 25 18 450 Div2 225 MHz 100 MHz 2 75 MHz 1 112 5 MHz...

Page 111: ...e a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300 MHz the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be set to SYSCLK3 with the PLLDIV3 register set to 3 The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided by 4 5 The PLLDIV3 block that sets the divider ratio for SYSCLK...

Page 112: ...ource When the RMII interface is active the RMII 50 MHz reference clock is sourced either from an external clock on the RMII_MHZ_50_CLK pin or from SYSCLK7 as shown in Figure 6 5 The PINMUX9_23_20 bits in the pin multiplexing control 9 register PINMUX9 of the System Configuration Module control this clock selection PINMUX9_23_20 0 enables sourcing of the 50 MHz reference clock from an external sou...

Page 113: ... 2 Certain PLL configurations do not support a 50 MHz clock on SYSCLK7 Table 6 7 EMAC Reference Clock Frequencies OSCIN Frequency PLL Multiplier Register Setting Multiplier Frequency MHz Post Divider Mode 1 POSTDIV Output Frequency PLLDIV7 Register Setting SYSCLK7 25 24 600 Div2 300 MHz 5 50 MHz Div3 200 MHz 3 50 MHz Div4 150 MHz 2 50 MHz 25 18 450 Div2 225 MHz Not Applicable 2 Div3 150 MHz 2 50 M...

Page 114: ...rals Contained within Group Source of Peripheral Clock RTC Operates off of a dedicated 32 kHz crystal oscillator RTC 1 Fixed Frequency Peripherals As the name suggests fixed frequency peripherals have a fixed frequency They are fed the AUXCLK directly from the oscillator input Timers I2C0 Synchronous Peripherals Synchronous peripherals have their frequencies derived from the CPU clock frequency Th...

Page 115: ...ht 2013 2016 Texas Instruments Incorporated Phase Locked Loop Controller PLLC Chapter 7 SPRUH91D March 2013 Revised September 2016 Phase Locked Loop Controller PLLC Topic Page 7 1 Introduction 116 7 2 PLL0 Control 116 7 3 Locking Unlocking PLL Register Access 120 7 4 PLLC Registers 121 ...

Page 116: ...through the system PLL controller 0 PLLC0 registers Figure 7 1 shows the PLL0 in the device AUXCLK is the clock provided to the fixed clock domain The PLL0 multiplier is controlled by the PLLM bits in the PLL multiplier control register PLLM and is set to a default value of 0000 0013h at power up resulting in a PLL multiplier of 20 The PLL0 output clock may be divided down for slower device operat...

Page 117: ...PLLM PLLEN AUXCLK 0 1 PLL Post Div CLKMODE 1 0 Square Wave Crystal OSCIN OBSCLK Pin 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 OCSEL OCSRC OSCDIV A www ti com PLL0 Control 117 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Phase Locked Loop Controller PLLC Figure 7 1 PLL0 Struc...

Page 118: ... is not supported on the C6745 DSP On the C6747 DSP this is only available on the ZKB device package type Table 7 1 System PLLC0 Output Clocks Output Clock Used by Default Ratio relative to SYSCLK1 Notes SYSCLK1 DSP 1 Fixed Ratio SYSCLK2 EDMA DSP ports EMIFB bus ports eCAPs eHRPWMs eQEPs Shared RAM 1 LCDC 1 McASPs 2 SPIs MMC SD HPI 1 USB2 0 UARTs PRU 2 Fixed Ratio SYSCLK3 EMIFA 3 No Required Ratio...

Page 119: ...owing procedure to initialize the PLL 1 Clear the PLLEN bit in PLLCTL to 0 select PLL Bypass mode and reset the PLL by clearing PLLRST bit in PLLCTL Wait for 4 OSCIN cycles to ensure PLLC switches to bypass mode properly 2 Select the clock mode by programming the CLKMODE bit in PLLCTL a Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL PLLEN to take effect b PLLCTL EXTCLKSRC should be left to ...

Page 120: ...to initiate the divider change 1 Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress 2 Program the RATIO field in PLLDIVn with the desired divide factors 3 Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition 4 Wait for the GOSTAT bit in PLLSTAT to clear to 0 completion of divider change 7 3 Locking Unlocking PLL Register Acc...

Page 121: ...n 7 4 8 01C1 1120h PLLDIV3 PLL Controller Divider 3 Register Section 7 4 9 01C1 1124h OSCDIV 1 Oscillator Divider 1 Register OBSCLK Section 7 4 14 01C1 1128h POSTDIV PLL Post Divider Control Register Section 7 4 15 01C1 1138h PLLCMD PLL Controller Command Register Section 7 4 16 01C1 113Ch PLLSTAT PLL Controller Status Register Section 7 4 17 01C1 1140h ALNCTL PLL Controller Clock Align Control Re...

Page 122: ...PE latches the cause of the last reset If multiple reset sources are asserted simultaneously RSTYPE records the reset source that deasserts last If multiple reset sources are asserted and deasserted simultaneously RSTYPE latches the highest priority reset source Figure 7 3 Reset Type Status Register RSTYPE 31 16 Reserved R 0 15 3 2 1 0 Reserved PLLSWRST XWRST POR R 0 R 0 R 0 R 0 LEGEND R Read only...

Page 123: ...W 1 R W 0 R 0 R W 1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 5 PLL Control Register PLLCTL Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKMODE Reference Clock Selection 0 Internal oscillator crystal 1 Square wave 7 6 Reserved 1 Reserved 5 PLLENSRC 0 This bit must be cleared before PLLEN will have any effect 4 Reserved 1 Reserved Write the de...

Page 124: ...o its normal function of being a direct input clock divider The OCSEL is shown in Figure 7 5 and described in Table 7 6 Figure 7 5 OBSCLK Select Register OCSEL 31 16 Reserved R 0 15 5 4 0 Reserved OCSRC R 0 R W 14h LEGEND R W Read Write R Read only n value after reset Table 7 6 OBSCLK Select Register OCSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 OCSRC 0 1Fh OBSC...

Page 125: ...ltiplier Value PLLM 1 The valid range of multiplier values for a given OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency See the device specific data manual for PLL VCO frequency specification limits 7 4 6 PLL Pre Divider Control Register PREDIV The PLL pre divider control register PREDIV is shown in Figure 7 7 and described in Table 7 8 Figure 7 7 PLL Pre Divid...

Page 126: ... Description 31 16 Reserved 0 Reserved 15 D1EN Divider Enable 0 Disable 1 Enable 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 0 PLL divide by 1 7 4 8 PLL Controller Divider 2 Register PLLDIV2 The PLL controller divider 2 register PLLDIV2 is shown in Figure 7 9 and described in Table 7 10 Divider 2 controls the divider for SYSCLK2 Figure 7 9 PLL Con...

Page 127: ...ue Description 31 16 Reserved 0 Reserved 15 D3EN Divider Enable 0 Disable 1 Enable 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 2h PLL divide by 3 7 4 10 PLL Controller Divider 4 Register PLLDIV4 The PLL controller divider 4 register PLLDIV4 is shown inFigure 7 11 and described in Table 7 12 Divider 4 controls the divider for SYSCLK4 Figure 7 11 PL...

Page 128: ...lue Description 31 16 Reserved 0 Reserved 15 D5EN Divider Enable 0 Disable 1 Enable 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults 2 PLL divide by 3 7 4 12 PLL Controller Divider 6 Register PLLDIV6 The PLL controller divider 6 register PLLDIV6 is shown in Figure 7 13 and described in Table 7 14 Divider 6 controls the divider for SYSCLK6 Figure 7 13 PLL ...

Page 129: ...ibed in Table 7 15 Divider 7 controls the divider for SYSCLK7 Figure 7 14 PLL Controller Divider 7 Register PLLDIV7 31 16 Reserved R 0 15 14 5 4 0 D7EN Reserved RATIO R W 1 R 0 R W 5h LEGEND R W Read Write R Read only n value after reset Table 7 15 PLL Controller Divider 7 Register PLLDIV7 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 D7EN Divider Enable 0 Disable 1 E...

Page 130: ... The OSCDIV is shown in Figure 7 15 and described in Table 7 16 Figure 7 15 Oscillator Divider 1 Register OSCDIV 31 16 Reserved R 0 15 14 5 4 0 OD1EN Reserved RATIO R W 1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 16 Oscillator Divider 1 Register OSCDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 OD1EN Oscillator divider 1 enable 0 Oscil...

Page 131: ...d 0 Reserved 15 POSTDEN Post_Divider enable 0 Disable 1 Enable 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 1 PLL post divide by 2 7 4 16 PLL Controller Command Register PLLCMD The PLL controller command register PLLCMD is shown in Figure 7 17 and described in Table 7 18 contains command bits for various operations Writes of 1 initiate command writ...

Page 132: ...tatus Register PLLSTAT 31 16 Reserved R 0 15 3 2 1 0 Reserved STABLE Reserved GOSTAT R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 7 19 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 STABLE OSC counter done oscillator assumed to be stable By the time the device comes out of reset this bit should become 1 0 No 1 Yes 1 ...

Page 133: ...W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 20 PLL Controller Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 ALN7 SYSCLK7 needs to be aligned to others selected in this register 0 No 1 Yes 5 ALN6 SYSCLK6 needs to be aligned to others selected in this register 0 No 1 Yes 4 ALN5 SYSCLK5 needs...

Page 134: ...R 0 LEGEND R Read only n value after reset Table 7 21 PLLDIV Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 SYS7 SYSCLK7 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 5 SYS6 SYSCLK6 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 4 SYS5 SYSCLK5 divide ratio is modified 0 Ratio is not modifie...

Page 135: ...2 1 0 Reserved OBSEN 1 AUXEN R 0 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 22 Clock Enable Control Register CKEN Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSEN OBSCLK enable Actual OBSCLK status is shown in the clock status register CKSTAT This bit is not supported and is Reserved on the C6745 DSP Write the default value when modifyi...

Page 136: ... 22 Clock Status Register CKSTAT 31 16 Reserved R 0 15 1 0 Reserved OBSON 1 AUXEN R 0 R 1 R 1 LEGEND R Read only n value after reset Table 7 23 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSON OBSCLK on status OBSCLK is controlled in the oscillator divider 1 register OSCDIV and by the OBSEN bit in the clock enable control register CKEN Th...

Page 137: ...nEN bit in PLLDIVn default Figure 7 23 SYSCLK Status Register SYSTAT 31 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON R 0 R 1 R 1 R 1 R 1 R 1 R 1 R 1 LEGEND R W Read Write R Read only n value after reset Table 7 24 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 SYS7ON SYSCLK7 on status 0 Off 1 On 5 ...

Page 138: ...0 31 0 COUNT R 0 LEGEND R Read only n value after reset Table 7 25 Emulation Performance Counter 0 Register EMUCNT0 Field Descriptions Bit Field Value Description 31 0 COUNT 0 FFFF FFFFh Counter value for lower 64 bits 7 4 24 Emulation Performance Counter 1 Register EMUCNT1 The emulation performance counter 1 register EMUCNT1 is shown in Figure 7 25 and described in Table 7 26 EMUCNT1 is for emula...

Page 139: ...porated Power and Sleep Controller PSC Chapter 8 SPRUH91D March 2013 Revised September 2016 Power and Sleep Controller PSC Topic Page 8 1 Introduction 140 8 2 Power Domain and Module Topology 140 8 3 Executing State Transitions 144 8 4 IcePick Emulation Support in the PSC 145 8 5 PSC Interrupts 145 8 6 PSC Registers 148 ...

Page 140: ...s for the RAMs present in the DSP subsystem and the L3 RAM respectively Each PSC module controls clock states for several on the on chip modules controllers and interconnect components Table 8 1 and Table 8 2 lists the set of peripherals modules that are controlled by the PSC the power domain they are associated with the LPSC assignment and the default power on reset module states See the device s...

Page 141: ...lwaysON PD0 SwRstDisable 2 USB1 USB1 1 1 AlwaysON PD0 SwRstDisable 3 GPIO AlwaysON PD0 SwRstDisable 4 HPI 1 AlwaysON PD0 SwRstDisable 5 EMAC AlwaysON PD0 SwRstDisable 6 EMIFB BR20 AlwaysON PD0 SwRstDisable 7 McASP0 McASP0 FIFO AlwaysON PD0 SwRstDisable 8 McASP1 McASP1 FIFO AlwaysON PD0 SwRstDisable 9 McASP2 McASP2 FIFO 1 AlwaysON PD0 SwRstDisable 10 SPI1 AlwaysON PD0 SwRstDisable 11 I2C1 AlwaysON ...

Page 142: ...tes are essentially a combination of the module reset asserted or de asserted and module clock on enabled or off disabled The various module states are defined in Table 8 3 The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in Auto Sleep mode it will transition back to the clock disabled state automatically sleep after servicing the internal read w...

Page 143: ... has some cycle latency associated with it It is not envisioned to use this mode when peripherals are fully operational and moving data See Section 8 2 2 1 for additional considerations constraints limitations around this mode Auto Wake De asserted Off A module in the Auto Wake state also has its module reset de asserted and its module clock disabled similar to the Disable state However this is a ...

Page 144: ...steps you must take before you can invoke the PSC module state transition See the individual peripheral user guides for more details For example the external memory controller requires that you first place the SDRAM memory in self refresh mode before you invoke the PSC module state transitions if you want to maintain the memory contents The following procedure is directly applicable for all module...

Page 145: ...ed local and module resets NOTE When emulation tools remove the above commands the PSC immediately executes a state transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in MDCTLn as set by software 8 5 PSC Interrupts The PSC has an interrupt that is tied to the core interrupt controller This interrupt is named PSCINT in the interrupt map The PSC interrupt is generated ...

Page 146: ... reflected in the EMURST bit in the module status register MDSTATn In particular a module local reset emulation event occurs under the following conditions When assert reset is asserted by emulation although software de asserted the local reset When wait reset is asserted by emulation When block reset is asserted by emulation and software attempts to change the state of local reset 8 5 2 Interrupt...

Page 147: ...e interrupt events that you want NOTE The PSC interrupt is sent to the device interrupt controller when at least one enabled event becomes active 2 Enable the power sleep controller interrupt PSCn_ALLINT in the device interrupt controller To interrupt the CPU PSCn_ALLINT must be enabled in the device interrupt controller See the DSP Subsystem chapter for more information on interrupts The CPU ente...

Page 148: ...8 6 15 01C1 0404h PDCFG1 Power Domain 1 Configuration Register Section 8 6 16 01C1 0800h 01C1 083Ch MDSTAT0 MDSTAT15 Module Status n Register modules 0 15 Section 8 6 17 01C1 0A00h 01C1 0A3Ch MDCTL0 MDCTL15 Module Control n Register modules 0 15 Section 8 6 18 Table 8 7 Power and Sleep Controller 1 PSC1 Registers Address Acronym Register Description Section 01E2 7000h REVID Revision Identification...

Page 149: ...n Identification Register REVID Field Descriptions Bit Field Value Description 31 0 REV 4482 3A00h Peripheral revision ID 8 6 2 Interrupt Evaluation Register INTEVAL The interrupt evaluation register INTEVAL is shown in Figure 8 2 and described in Table 8 9 Figure 8 2 Interrupt Evaluation Register INTEVAL 31 16 Reserved R 0 15 1 0 Reserved ALLEV R 0 W 0 LEGEND R Read only W Write only n value afte...

Page 150: ...0 R 0 LEGEND R Read only n value after reset Table 8 10 PSC0 Module Error Pending Register 0 MERRPR0 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 M 15 Module interrupt status bit for module 15 DSP 0 Module 15 does not have an error condition 1 Module 15 has an error condition See the module status 15 register MDSTAT15 for the error condition 14 0 Reserved 0 Reserved ...

Page 151: ...reset Table 8 11 PSC0 Module Error Clear Register 0 MERRCR0 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 M 15 Clears the interrupt status bit M 15 set in the PSC0 module error pending register 0 MERRPR0 and the interrupt status bits set in the module status 15 register MDSTAT15 0 A write of 0 has no effect 1 A write of 1 clears the M 15 bit in MERRPR0 and the EMUIHB ...

Page 152: ...have an error condition 1 RAM Pseudo power domain has an error condition See the power domain 1 status register PDSTAT1 for the error condition 0 Reserved 0 Reserved 8 6 8 Power Error Clear Register PERRCR The power error clear register PERRCR is shown in Figure 8 8 and described in Table 8 13 Figure 8 8 Power Error Clear Register PERRCR 31 16 Reserved R 0 15 2 1 0 Reserved P 1 Rsvd R 0 W 0 R 0 LE...

Page 153: ... Pseudo PD1 power domain GO transition command 0 A write of 0 has no effect 1 A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain including PDCTL NEXT for this domain and MDCTL NEXT for all the modules residing on this domain If any of the NEXT fields are not matching the corresponding current state PDSTAT STATE MDSTAT STATE the PSC will transition those respe...

Page 154: ...15 2 1 0 Reserved GOSTAT 1 GOSTAT 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 8 15 Power Domain Transition Status Register PTSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 GOSTAT 1 RAM Pseudo PD1 power domain transition status 0 No transition in progress 1 RAM Pseudo power domain is transitioning that is either the power domain is transitioning or mod...

Page 155: ...ield Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active No emulation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Do...

Page 156: ...ield Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active No emulation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Do...

Page 157: ...reset Table 8 18 Power Domain 0 Control Register PDCTL0 Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 WAKECNT 0 FFh RAM wake count delay value Not recommended to change the default value 1Fh Bits 23 30 GOOD2ACCESS wake delay Bits 19 16 ON2GOOD wake delay 15 12 PDMODE 0 Fh Power down mode 0 Eh Reserved Fh Core on RAM array on RAM periphery on 11 10 Reserved 0 Reserv...

Page 158: ...ay value Not recommended to change the default value 1Fh Bits 23 30 GOOD2ACCESS wake delay Bits 19 16 ON2GOOD wake delay 15 12 PDMODE 0 Fh Power down mode 0 Core off RAM array off RAM periphery off 1h Core off RAM array retention RAM periphery off deep sleep 2h 3h Reserved 4h Core retention RAM array off RAM periphery off 5h Core retention RAM array retention RAM periphery off deep sleep 6h 7h Res...

Page 159: ... 3 2 1 0 Reserved PD_LOCK ICEPICK RAM_PSM ALWAYSON R 0 R 1 R 1 R 0 R 1 LEGEND R Read only n value after reset Table 8 20 Power Domain 0 Configuration Register PDCFG0 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not...

Page 160: ... 3 2 1 0 Reserved PD_LOCK ICEPICK RAM_PSM ALWAYSON R 0 R 1 R 1 R 0 R 1 LEGEND R Read only n value after reset Table 8 21 Power Domain 1 Configuration Register PDCFG1 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not...

Page 161: ...nt you must set the EMUIHBIE bit in MDCTL15 16 EMURST Emulation alters module reset This bit applies to DSP module module 15 This field is 0 for all other modules 0 No emulation altering user desired module reset state 1 Emulation altered user desired module reset state If you desire to generate a PSCINT upon this event you must set the EMURSTIE bit in the module control 15 register MDCTL15 15 13 ...

Page 162: ...rces the module state programmed in the NEXT bit in the module control 15 register MDCTL15 ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module Note It is not recommended to use the FORCE bit to disable the module clock unless specified 0 Force is disabled 1 Force is enabled 30 11 Reserved 0 Reserved 10 EMUIHBIE Interrupt e...

Page 163: ...ND R W Read Write R Read only n value after reset Table 8 24 PSC1 Module Control n Register MDCTLn Field Descriptions Bit Field Value Description 31 FORCE Force enable This bit forces the module state programmed in the NEXT bit in the module control 15 register MDCTL15 ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module No...

Page 164: ...anagement Chapter 9 SPRUH91D March 2013 Revised September 2016 Power Management Topic Page 9 1 Introduction 165 9 2 Power Consumption Overview 165 9 3 PSC and PLLC Overview 165 9 4 Features 166 9 5 Clock Management 167 9 6 DSP Sleep Mode Management 168 9 7 RTC Only Mode 168 9 8 Additional Peripheral Power Management Considerations 169 ...

Page 165: ...gnificant impact on overall power consumption and thus on the battery life Dynamic power can be reduced by scaling the operating voltage when the performance requirements are not that high and the device can be operated at a corresponding lower frequency The capacitance is the capacitance of the switching nodes or the load capacitances on the switching I O pins The static power as the name suggest...

Page 166: ...ou to slow down the clocks to reduce the dynamic power Table 9 1 describes the power management features 1 This peripheral is not supported on the C6745 DSP Table 9 1 Power Management Features Power Management Description Features Clock Management PLL power down The PLL can be powered down and run in bypass modes when not in use Reduces the dynamic power consumption of the core Module clock ON OFF...

Page 167: ...sideration must be given to DSP clock on off The procedure to turn the core clock on off is further described in Additionally some peripherals implement additional power saving features by automatically shutting of clock to components within the module when the logic is not active This is transparent to you but reduces overall dynamic power consumption when modules are not active 9 5 2 Module Cloc...

Page 168: ... the IDLE instruction to put only the CPU in idle mode For information on putting the C674x megamodule in the low power mode using the PDC see the TMS320C674x DSP Megamodule Reference Guide SPRUFK5 9 7 RTC Only Mode NOTE To put the device in RTC only mode there is no software control sequence You can put the device in the RTC only mode by removing the power supply from all core and I O logic excep...

Page 169: ...u can put the USB2 0 PHY and OTG module in the lowest power state when not in use by writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the chip configuration 2 register CFGCHIP2 of the system configuration SYSCFG module NOTE If the USB1 1 subsystem is used and the 48 MHz clock input is sourced from the USB2 0 PHY then the USB2 0 PHY should not be powered down 9 8 2 EMIFB Memory Clock Gating ...

Page 170: ...16 Texas Instruments Incorporated System Configuration SYSCFG Module Chapter 10 SPRUH91D March 2013 Revised September 2016 System Configuration SYSCFG Module Topic Page 10 1 Introduction 171 10 2 Protection 172 10 3 Master Priority Control 174 10 4 Interrupt Support 175 10 5 SYSCFG Registers 176 ...

Page 171: ...pend control for peripherals that support the feature Special Peripheral Status and Control Locking of PLL control settings Default burst size configuration for EDMA3 transfer controllers Event source selection for the eCAP peripheral input capture McASP AMUTEIN selection and clearing of AMUTE USB PHY Control Clock source selection for EMIFA and EMIFB HPI Control this peripheral is not supported o...

Page 172: ...IPREVID Silicon Revision Identification Register Privileged mode 38h KICK0R Kick 0 Register Privileged mode 3Ch KICK1R Kick 1 Register Privileged mode 44h HOST1CFG Host 1 Configuration Register E0h IRAWSTAT Interrupt Raw Status Set Register Privileged mode E4h IENSTAT Interrupt Enable Status Clear Register Privileged mode E8h IENSET Interrupt Enable Register Privileged mode ECh IENCLR Interrupt En...

Page 173: ...e are listed in Section 10 5 See the TMS320C674x DSP CPU and Instruction Set Reference Guide SPRUFE8 for details on privilege levels 10 2 1 2 Kicker Mechanism Protection NOTE The Kick 0 and Kick 1 registers can only be accessed in privileged mode the host needs to be in Supervisor mode Any number of accesses may be performed to the SYSCFG module while the module is unlocked The SYSCFG module remai...

Page 174: ...r ID is shown in Table 10 2 See the device specific data manual to determine the masters present on your device Each switched central resource SCR performs prioritization based on priority level of the master that sends the read write requests For all peripherals ports classified as masters on the device the priority is programmed in the master priority registers MSTPRI0 3 in the SYSCFG modules Th...

Page 175: ...2 0 DMA 4 MSTPRI2 USB1 1 5 4 MSTPRI2 LCDC 5 6 5 MSTPRI2 HPI 5 6 MSTPRI2 10 4 Interrupt Support 10 4 1 Interrupt Events and Requests The SYSCFG module generates two interrupts an address error interrupt BOOTCFG_ADDR_ERR and a protection interrupt BOOTCFG_PROT_ERR The BOOTCFG_ADDR_ERR is generated when there is an addressing violation due to an access to a non existent location in the SYSCFG registe...

Page 176: ...1C1 4110h MSTPRI0 Master Priority 0 Register Section 10 5 9 1 01C1 4114h MSTPRI1 Master Priority 1 Register Section 10 5 9 2 01C1 4118h MSTPRI2 Master Priority 2 Register Section 10 5 9 3 01C1 4120h PINMUX0 Pin Multiplexing Control 0 Register Section 10 5 10 1 01C1 4124h PINMUX1 Pin Multiplexing Control 1 Register Section 10 5 10 2 01C1 4128h PINMUX2 Pin Multiplexing Control 2 Register Section 10 ...

Page 177: ...sion identification register REVID provides the revision information for the SYSCFG module The REVID is shown in Figure 10 1 and described in Table 10 5 Figure 10 1 Revision Identification Register REVID 31 0 REV R 4E84 0102h LEGEND R Read only n value after reset Table 10 5 Revision Identification Register REVID Field Descriptions Bit Field Value Description 31 0 REV 4E84 0102h Revision ID Revisi...

Page 178: ...le 10 7 Boot Configuration Register BOOTCFG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BOOTMODE 0 FFFFh Boot Mode This reflects the state of the boot mode pins 10 5 4 Silicon Revision Identification Register CHIPREVID The silicon revision identification register CHIPREVID provides software readable silicon revision information for the device The CHIPREVID is show...

Page 179: ...n and block out any write accesses to registers in the SYSCFG module 10 5 5 1 Kick 0 Register KICK0R The KICK0R is shown in Figure 10 5 and described in Table 10 9 Figure 10 5 Kick 0 Register KICK0R 31 0 KICK1 R W 0 LEGEND R W Read Write n value after reset Table 10 9 Kick 0 Register KICK0R Field Descriptions Bit Field Value Description 31 0 KICK0 0 FFFF FFFFh KICK0R allows writing to unlock the k...

Page 180: ...modified to allow execution from an alternate location after a module level or local reset on the DSP The HOST1CFG is shown in Figure 10 7 and described in Table 10 11 Figure 10 7 Host 1 Configuration Register HOST1CFG 31 16 DSP_ISTP_RST_VAL R W 0 1C00h 15 10 9 1 0 DSP_ISTP_RST_VAL Reserved BOOTRDY R W 0 1C00h R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 10 11 Host 1 Confi...

Page 181: ...he interrupt and allows setting of the interrupt status The IRAWSTAT is shown in Figure 10 8 and described in Table 10 12 Figure 10 8 Interrupt Raw Status Set Register IRAWSTAT 31 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 12 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Descriptio...

Page 182: ...1 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 13 Interrupt Enable Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always read 0 1 ADDRERR Addressing violation error Reading this bit field reflects the interrupt enabled status 0 Indicates the interrupt is not se...

Page 183: ...on error 0 Writing a 0 has not effect 1 Writing a 1 enables this interrupt 0 PROTERR_EN Protection violation error 0 Writing a 0 has not effect 1 Writing a 1 enables this interrupt 10 5 7 4 Interrupt Enable Clear Register IENCLR The interrupt enable clear register IENCLR allows clearing disable the interrupt for address and or protection violation condition It also shows the value of the interrupt...

Page 184: ...d EOIVECT R 0 W 0 LEGEND R Read only W Write only n value after reset Table 10 16 End of Interrupt Register EOI Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always read 0 7 0 EOIVECT 0 FFh EOI vector value Write the interrupt distribution value of the chip 10 5 8 Fault Registers The fault registers are a group of registers responsible for capturing the details on the fau...

Page 185: ...8 Figure 10 14 Fault Status Register FLTSTAT 31 24 23 16 ID MSTID R 0 R 0 15 13 12 9 8 6 5 0 Reserved PRIVID Reserved TYPE R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 10 18 Fault Status Register FLTSTAT Field Descriptions Bit Field Value Description 31 24 ID 0 FFh Transfer ID of the first fault transfer 23 16 MSTID 0 FFh Master ID of the first fault transfer 15 13 Reserved 0 Reser...

Page 186: ...odifying this register 30 28 Reserved 4h Reserved Write the default value when modifying this register 27 Reserved 0 Reserved Write the default value when modifying this register 26 24 Reserved 4h Reserved Write the default value when modifying this register 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 4h Reserved Write the default value when modifying...

Page 187: ...8 Reserved 4h Reserved Write the default value when modifying this register 27 Reserved 0 Reserved Write the default value when modifying this register 26 24 Reserved 4h Reserved Write the default value when modifying this register 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 4h Reserved Write the default value when modifying this register 19 Reserved ...

Page 188: ... the C6745 DSP 27 Reserved 0 Reserved Write the default value when modifying this register 26 24 USB1 0 7h USB1 USB1 1 priority Bit 0 priority 0 highest bit 7h priority 7 lowest This peripheral is not supported on the C6745 DSP 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 UHPI 0 7h HPI priority Bit 0 priority 0 highest bit 7h priority 7 lowest This peripheral i...

Page 189: ...s or that interface mode is being used Detailed information about the pin multiplexing and control is covered in the device specific data manual Access to the pin multiplexing utility is available in OMAP L137 TMS320C6747 6745 6743 Pin Multiplexing Utility Application Report SPRAB06 10 5 10 1 Pin Multiplexing Control 0 Register PINMUX0 Figure 10 18 Pin Multiplexing Control 0 Register PINMUX0 31 28...

Page 190: ...V4P5 or SYSCLK5 CLK2 3h Fh Reserved 11 8 PINMUX0_11_8 C13 88 EMB_SDCKE Control 0 Pin is 3 stated 1h Selects Function EMB_SDCKE 2h Fh Reserved 7 4 PINMUX0_7_4 J5 GP7 15 EMU 0 Control 0 Pin is 3 stated 1h Selects Function GP7 15 2h 7h Reserved 8h Selects Function EMU 0 9h Fh Reserved 3 0 PINMUX0_3_0 K1 157 GP7 14 Control GP7 14 is initially configured as a reserved function after reset and will not ...

Page 191: ...e is not supported on the C6747 DSP Table 10 23 Pin Multiplexing Control 1 Register PINMUX1 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX1_31_28 C11 97 EMB_A 5 GP7 7 Control 0 Pin is 3 stated 1h Selects Function EMB_A 5 2h 7h Reserved 8h Selects Function GP7 7 9h Fh Reserved 27 24 PINMUX1_27_24 D11 98 EMB_A 4 GP7 6 Control 0 Pin is 3 stated 1h Selects Function EM...

Page 192: ... ZKB Ball 1 PTP Pin 2 Value Description 11 8 PINMUX1_11_8 D10 103 EMB_A 0 GP7 2 Control 0 Pin is 3 stated 1h Selects Function EMB_A 0 2h 7h Reserved 8h Selects Function GP7 2 9h Fh Reserved 7 4 PINMUX1_7_4 C9 107 EMB_BA 0 GP7 1 Control 0 Pin is 3 stated 1h Selects Function EMB_BA 0 2h 7h Reserved 8h Selects Function GP7 1 9h Fh Reserved 3 0 PINMUX1_3_0 B9 106 EMB_BA 1 GP7 0 Control 0 Pin is 3 stat...

Page 193: ...45 DSP this package is not supported on the C6747 DSP Table 10 24 Pin Multiplexing Control 2 Register PINMUX2 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX2_31_28 G14 EMB_D 31 Control 0 Pin is 3 stated 1h Selects Function EMB_D 31 2h Fh Reserved 27 24 PINMUX2_27_24 B15 89 EMB_A 12 GP3 13 Control 0 Pin is 3 stated 1h Selects Function EMB_A 12 2h 7h Reserved 8h Sel...

Page 194: ...d ZKB Ball 1 PTP Pin 2 Value Description 11 8 PINMUX2_11_8 D12 94 EMB_A 8 GP7 10 Control 0 Pin is 3 stated 1h Selects Function EMB_A 8 2h 7h Reserved 8h Selects Function GP7 10 9h Fh Reserved 7 4 PINMUX2_7_4 A11 95 EMB_A 7 GP7 9 Control 0 Pin is 3 stated 1h Selects Function EMB_A 7 2h 7h Reserved 8h Selects Function GP7 9 9h Fh Reserved 3 0 PINMUX2_3_0 B11 96 EMB_A 6 GP7 8 Control 0 Pin is 3 state...

Page 195: ...747 DSP Table 10 25 Pin Multiplexing Control 3 Register PINMUX3 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX3_31_28 L15 EMB_D 23 Control 0 Pin is 3 stated 1h Selects Function EMB_D 23 2h Fh Reserved 27 24 PINMUX3_27_24 A13 EMB_D 24 Control 0 Pin is 3 stated 1h Selects Function EMB_D 24 2h Fh Reserved 23 20 PINMUX3_23_20 B14 EMB_D 25 Control 0 Pin is 3 stated 1h ...

Page 196: ...DSP Table 10 26 Pin Multiplexing Control 4 Register PINMUX4 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX4_31_28 A12 EMB_WE_DQM 3 Control 0 Pin is 3 stated 1h Selects Function EMB_WE_DQM 3 2h Fh Reserved 27 24 PINMUX4_27_24 G15 EMB_D 16 Control 0 Pin is 3 stated 1h Selects Function EMB_D 16 2h Fh Reserved 23 20 PINMUX4_23_20 H14 EMB_D 17 Control 0 Pin is 3 stated...

Page 197: ...ge is not supported on the C6747 DSP Table 10 27 Pin Multiplexing Control 5 Register PINMUX5 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX5_31_28 J15 63 EMB_D 6 GP6 6 Control 0 Pin is 3 stated 1h Selects Function EMB_D 6 2h 7h Reserved 8h Selects Function GP6 6 9h Fh Reserved 27 24 PINMUX5_27_24 J13 64 EMB_D 5 GP6 5 Control 0 Pin is 3 stated 1h Selects Function E...

Page 198: ...ns continued Bit Field ZKB Ball 1 PTP Pin 2 Value Description 11 8 PINMUX5_11_8 G13 72 EMB_D 1 GP6 1 Control 0 Pin is 3 stated 1h Selects Function EMB_D 1 2h 7h Reserved 8h Selects Function GP6 1 9h Fh Reserved 7 4 PINMUX5_7_4 F16 73 EMB_D 0 GP6 0 Control 0 Pin is 3 stated 1h Selects Function EMB_D 0 2h 7h Reserved 8h Selects Function GP6 0 9h Fh Reserved 3 0 PINMUX5_3_0 B13 EMB_WE_DQM 2 Control 0...

Page 199: ...supported on the C6747 DSP Table 10 28 Pin Multiplexing Control 6 Register PINMUX6 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX6_31_28 E16 76 EMB_D 14 GP6 14 Control 0 Pin is 3 stated 1h Selects Function EMB_D 14 2h 7h Reserved 8h Selects Function GP6 14 9h Fh Reserved 27 24 PINMUX6_27_24 E13 78 EMB_D 13 GP6 13 Control 0 Pin is 3 stated 1h Selects Function EMB_D...

Page 200: ...ld ZKB Ball 1 PTP Pin 2 Value Description 11 8 PINMUX6_11_8 D13 83 EMB_D 9 GP6 9 Control 0 Pin is 3 stated 1h Selects Function EMB_D 9 2h 7h Reserved 8h Selects Function GP6 9 9h Fh Reserved 7 4 PINMUX6_7_4 C16 84 EMB_D 8 GP6 8 Control 0 Pin is 3 stated 1h Selects Function EMB_D 8 2h 7h Reserved 8h Selects Function GP6 8 9h Fh Reserved 3 0 PINMUX6_3_0 J16 62 EMB_D 7 GP6 7 Control 0 Pin is 3 stated...

Page 201: ... Control 7 Register PINMUX7 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX7_31_28 N4 9 SPI0_SCS 0 UART0_RTS EQEP0B GP5 4 BOOT 4 Control 0 Pin is 3 stated 1h Selects Function SPI0_SCS 0 2h Selects Function UART0_RTS 3h Reserved 4h Selects Function EQEP0B 5h 7h Reserved 8h Selects Function GP5 4 9h Fh Reserved 27 24 PINMUX7_27_24 R5 12 SPI0_ENA UART0_CTS EQEP0A GP5 ...

Page 202: ... is 3 stated 1h Selects Function SPI0_SOMI 0 2h Selects Function EQEP0I 3h 7h Reserved 8h Selects Function GP5 0 9h Fh Reserved 11 8 PINMUX7_11_8 K14 60 EMB_WE_DQM 0 GP5 15 Control 0 Pin is 3 stated 1h Selects Function EMB_WE_DQM 0 2h 7h Reserved 8h Selects Function GP5 15 9h Fh Reserved 7 4 PINMUX7_7_4 C15 85 EMB_WE_DQM 1 GP5 14 Control 0 Pin is 3 stated 1h Selects Function EMB_WE_DQM 1 2h 7h Res...

Page 203: ...kage is not supported on the C6747 DSP Table 10 30 Pin Multiplexing Control 8 Register PINMUX8 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX8_31_28 R4 7 SPI1_ENA UART2_RXD GP5 12 Control 0 Pin is 3 stated 1h Selects Function SPI1_ENA 2h Selects Function UART2_RXD 3h 7h Reserved 8h Selects Function GP5 12 9h Fh Reserved 27 24 PINMUX8_27_24 T4 6 AXR1 11 GP5 11 Cont...

Page 204: ...eserved 4h Selects Function TM64P0_IN12 5h 7h Reserved 8h Selects Function GP5 8 9h Fh Reserved 11 8 PINMUX8_11_8 T6 16 SPI1_CLK EQEP1S GP5 7 BOOT 7 Control 0 Pin is 3 stated 1h Selects Function SPI1_CLK 2h Selects Function EQEP1S 3h 7h Reserved 8h Selects Function GP5 7 9h Fh Reserved 7 4 PINMUX8_7_4 N5 14 SPI1_SIMO 0 I2C1_SDA GP5 6 BOOT 6 Control 0 Pin is 3 stated 1h Selects Function SPI1_SIMO 0...

Page 205: ... Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX9_31_28 C4 131 AFSR0 GP3 12 Control 0 Pin is 3 stated 1h Selects Function AFSR0 2h 7h Reserved 8h Selects Function GP3 12 9h Fh Reserved 27 24 PINMUX9_27_24 B4 130 ACLKR0 ECAP1 APWM1 GP2 15 Control 0 Pin is 3 stated 1h Selects Function ACLKR0 2h Selects Function ECAP1 APWM1 3h 7h Reserved 8h Selects Function GP2 15 9h...

Page 206: ...0 APWM0 3h 7h Reserved 8h Selects Function GP2 12 9h Fh Reserved 11 8 PINMUX9_11_8 B5 125 AHCLKX0 AHCLKX2 USB_REFCLKIN GP2 11 Control 0 Pin is 3 stated 1h Selects Function AHCLKX0 2h Selects Function AHCLKX2 3h Reserved 4h Selects Function USB_REFCLKIN 5h 7h Reserved 8h Selects Function GP2 11 9h Fh Reserved 7 4 PINMUX9_7_4 E4 USB0_DRVVBUS GP4 15 Control 0 Pin is 3 stated 1h Selects Function USB0_...

Page 207: ...n the C6745 DSP this package is not supported on the C6747 DSP Table 10 32 Pin Multiplexing Control 10 Register PINMUX10 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX10_31_28 D7 118 AXR0 6 RMII_RXER 0 ACLKR2 GP3 6 Control 0 Pin is 3 stated 1h Selects Function AXR0 6 2h Selects Function RMII_RXER 0 3h Reserved 4h Selects Function ACLKR2 5h 7h Reserved 8h Selects F...

Page 208: ...XR2 3 GP3 2 Control 0 Pin is 3 stated 1h Selects Function AXR0 2 2h Selects Function RMII_TXEN 3h Reserved 4h Selects Function AXR2 3 5h 7h Reserved 8h Selects Function GP3 2 9h Fh Reserved 11 8 PINMUX10_11_8 C8 112 AXR0 1 RMII_TXD 1 ACLKX2 GP3 1 Control 0 Pin is 3 stated 1h Selects Function AXR0 1 2h Selects Function RMII_TXD 1 3h Reserved 4h Selects Function ACLKX2 5h 7h Reserved 8h Selects Func...

Page 209: ... C6747 DSP Table 10 33 Pin Multiplexing Control 11 Register PINMUX11 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX11_31_28 K4 163 AFSX1 EPWMSYNCI EPWMSYNC0 GP4 10 Control 0 Pin is 3 stated 1h Selects Function AFSX1 2h Selects Function EPWMSYNCI 3h Reserved 4h Selects Function EPWMSYNC0 5h 7h Reserved 8h Selects Function GP4 10 9h Fh Reserved 27 24 PINMUX11_27_24 ...

Page 210: ... 2h Selects Function AXR0 10 3h 7h Reserved 8h Selects Function GP3 10 9h Fh Reserved 11 8 PINMUX11_11_8 C6 122 UART1_RXD AXR0 9 GP3 9 Control 0 Pin is 3 stated 1h Selects Function UART1_RXD 2h Selects Function AXR0 9 3h 7h Reserved 8h Selects Function GP3 9 9h Fh Reserved 7 4 PINMUX11_7_4 B6 121 AXR0 8 MDIO_D GP3 8 Control 0 Pin is 3 stated 1h Selects Function AXR0 8 2h Selects Function MDIO_D 3h...

Page 211: ...6747 DSP Table 10 34 Pin Multiplexing Control 12 Register PINMUX12 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX12_31_28 P1 174 AXR1 3 EQEP1A GP4 3 Control 0 Pin is 3 stated 1h Selects Function AXR1 3 2h Selects Function EQEP1A 3h 7h Reserved 8h Selects Function GP4 3 9h Fh Reserved 27 24 PINMUX12_27_24 P2 175 AXR1 2 GP4 2 Control 0 Pin is 3 stated 1h Selects Fun...

Page 212: ...n 2 Value Description 11 8 PINMUX12_11_8 L3 166 AFSR1 GP4 13 Control 0 Pin is 3 stated 1h Selects Function AFSR1 2h 7h Reserved 8h Selects Function GP4 13 9h Fh Reserved 7 4 PINMUX12_7_4 L2 165 ACLKR1 ECAP2 APWM2 GP4 12 Control 0 Pin is 3 stated 1h Selects Function ACLKR1 2h Selects Function ECAP2 APWM2 3h 7h Reserved 8h Selects Function GP4 12 9h Fh Reserved 3 0 PINMUX12_3_0 L1 AHCLKR1 GP4 11 Con...

Page 213: ...SP Table 10 35 Pin Multiplexing Control 13 Register PINMUX13 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX13_31_28 R15 45 EMA_D 1 MMCSD_DAT 1 UHPI_HD 1 GP0 1 Control 0 Pin is 3 stated 1h Selects Function EMA_D 1 2h Selects Function MMCSD_DAT 1 3h Reserved 4h Selects Function UHPI_HD 1 5h 7h Reserved 8h Selects Function GP0 1 9h Fh Reserved 27 24 PINMUX13_27_24 T1...

Page 214: ... 7 2h Selects Function EPWM1B 3h 7h Reserved 8h Selects Function GP4 7 9h Fh Reserved 11 8 PINMUX13_11_8 M4 170 AXR1 6 EPWM2A GP4 6 Control 0 Pin is 3 stated 1h Selects Function AXR1 6 2h Selects Function EPWM2A 3h 7h Reserved 8h Selects Function GP4 6 9h Fh Reserved 7 4 PINMUX13_7_4 N1 171 AXR1 5 EPWM2B GP4 5 Control 0 Pin is 3 stated 1h Selects Function AXR1 5 2h Selects Function EPWM2B 3h 7h Re...

Page 215: ...745 DSP this package is not supported on the C6747 DSP Table 10 36 Pin Multiplexing Control 14 Register PINMUX14 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX14_31_28 T14 EMA_D 9 UHPI_HD 9 LCD_D 9 GP0 9 Control 0 Pin is 3 stated 1h Selects Function EMA_D 9 2h Selects Function UHPI_HD 9 3h Reserved 4h Selects Function LCD_D 9 5h 7h Reserved 8h Selects Function GP0...

Page 216: ...unction EMA_D 5 2h Selects Function MMCSD_DAT 5 3h Reserved 4h Selects Function UHPI_HD 5 5h 7h Reserved 8h Selects Function GP0 5 9h Fh Reserved 11 8 PINMUX14_11_8 P13 49 EMA_D 4 MMCSD_DAT 4 UHPI_HD 4 GP0 4 Control 0 Pin is 3 stated 1h Selects Function EMA_D 4 2h Selects Function MMCSD_DAT 4 3h Reserved 4h Selects Function UHPI_HD 4 5h 7h Reserved 8h Selects Function GP0 4 9h Fh Reserved 7 4 PINM...

Page 217: ...s only available on the C6745 DSP this package is not supported on the C6747 DSP Table 10 37 Pin Multiplexing Control 15 Register PINMUX15 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX15_31_28 R9 30 EMA_A 1 MMCSD_CLK UHPI_HCNTL0 GP1 1 Control 0 Pin is 3 stated 1h Selects Function EMA_A 1 2h Selects Function MMCSD_CLK 3h Reserved 4h Selects Function UHPI_HCNTL0 5h...

Page 218: ...Function EMA_D 13 2h Selects Function UHPI_HD 13 3h Reserved 4h Selects Function LCD_D 13 5h 7h Reserved 8h Selects Function GP0 13 9h Fh Reserved 11 8 PINMUX15_11_8 P14 EMA_D 12 UHPI_HD 12 LCD_D 12 GP0 12 Control 0 Pin is 3 stated 1h Selects Function EMA_D 12 2h Selects Function UHPI_HD 12 3h Reserved 4h Selects Function LCD_D 12 5h 7h Reserved 8h Selects Function GP0 12 9h Fh Reserved 7 4 PINMUX...

Page 219: ...ackage is not supported on the C6747 DSP Table 10 38 Pin Multiplexing Control 16 Register PINMUX16 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX16_31_28 R11 40 EMA_A 9 LCD_HSYNC GP1 9 Control 0 Pin is 3 stated 1h Selects Function EMA_A 9 2h Selects Function LCD_HSYNC 3h 7h Reserved 8h Selects Function GP1 9 9h Fh Reserved 27 24 PINMUX16_27_24 T11 39 EMA_A 8 LCD_P...

Page 220: ...7h Reserved 8h Selects Function GP1 5 9h Fh Reserved 11 8 PINMUX16_11_8 T10 34 EMA_A 4 LCD_D 3 GP1 4 Control 0 Pin is 3 stated 1h Selects Function EMA_A 4 2h Selects Function LCD_D 3 3h 7h Reserved 8h Selects Function GP1 4 9h Fh Reserved 7 4 PINMUX16_7_4 N9 32 EMA_A 3 LCD_D 6 GP1 3 Control 0 Pin is 3 stated 1h Selects Function EMA_A 3 2h Selects Function LCD_D 6 3h 7h Reserved 8h Selects Function...

Page 221: ...age is not supported on the C6747 DSP Table 10 39 Pin Multiplexing Control 17 Register PINMUX17 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX17_31_28 L16 EMA_CAS EMA_CS 4 GP2 1 Control 0 Pin is 3 stated 1h Selects Function EMA_CAS 2h Selects Function EMA_CS 4 3h 7h Reserved 8h Selects Function GP2 1 9h Fh Reserved 27 24 PINMUX17_27_24 T12 EMA_SDCKE GP2 0 Control ...

Page 222: ...eserved 4h Selects Function UHPI_HHWIL 5h 7h Reserved 8h Selects Function GP1 13 9h Fh Reserved 11 8 PINMUX17_11_8 N11 42 EMA_A 12 LCD_MCLK GP1 12 Control 0 Pin is 3 stated 1h Selects Function EMA_A 12 2h Selects Function LCD_MCLK 3h 7h Reserved 8h Selects Function GP1 12 9h Fh Reserved 7 4 PINMUX17_7_4 P11 41 EMA_A 11 LCD_AC_ENB_CS GP1 11 Control 0 Pin is 3 stated 1h Selects Function EMA_A 11 2h ...

Page 223: ...745 DSP this package is not supported on the C6747 DSP Table 10 40 Pin Multiplexing Control 18 Register PINMUX18 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 28 PINMUX18_31_28 M14 EMA_WE_DQM 0 UHPI_HINT AXR0 15 GP2 9 Control 0 Pin is 3 stated 1h Selects Function EMA_WE_DQM 0 2h Selects Function UHPI_HINT 3h Reserved 4h Selects Function AXR0 15 5h 7h Reserved 8h Selects Fu...

Page 224: ...PI_HCS GP2 5 BOOT 15 Control 0 Pin is 3 stated 1h Selects Function EMA_CS 2 2h Selects Function UHPI_HCS 3h 7h Reserved 8h Selects Function GP2 5 9h Fh Reserved 11 8 PINMUX18_11_8 T8 EMA_CS 0 UHPI_HAS GP2 4 Control 0 Pin is 3 stated 1h Selects Function EMA_CS 0 2h Selects Function UHPI_HAS 3h 7h Reserved 8h Selects Function GP2 4 9h Fh Reserved 7 4 PINMUX18_7_4 M13 55 EMA_WE UHPI_HRW AXR0 12 GP2 3...

Page 225: ...ead Write n value after reset 1 The ZKB ball package is only available on the C6747 DSP this package is not supported on the C6745 DSP 2 The PTP pin package is only available on the C6745 DSP this package is not supported on the C6747 DSP Table 10 41 Pin Multiplexing Control 19 Register PINMUX19 Field Descriptions Bit Field ZKB Ball 1 PTP Pin 2 Value Description 31 4 Reserved 0 Reserved 3 0 PINMUX...

Page 226: ...served USB0SRC Reserved R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 7 6 5 4 3 2 1 0 Reserved PRUSRC EMACSRC EQEP1SRC EQEP0SRC ECAP2SRC ECAP1SRC ECAP0SRC R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write n value after reset Table 10 42 Suspend Source Register SUSPSRC Field Descriptions Bit Field Value Description 31 29 Reserved 1 Reserved Write the default value to all bits ...

Page 227: ...ce This peripheral is not supported on the C6745 DSP 0 No emulation suspend 1 DSP is the source of the emulation suspend 11 10 Reserved 1 Reserved Write the default value to all bits when modifying this register 9 USB0SRC USB0 Emulation Suspend Source 0 No emulation suspend 1 DSP is the source of the emulation suspend 8 7 Reserved 1 Reserved Write the default value to all bits when modifying this ...

Page 228: ...so be used as status bits The CHIPSIG is shown in Figure 10 39 and described in Table 10 43 Figure 10 39 Chip Signal Register CHIPSIG 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved CHIPSIG4 CHIPSIG3 CHIPSIG2 Reserved R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 43 Chip Signal Register CHIPSIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 R...

Page 229: ... to determine when the interrupted processor has completed the interrupt service The CHIPSIG_CLR is shown in Figure 10 40 and described in Table 10 44 For more information on DSP interrupts see the DSP Subsystem chapter Figure 10 40 Chip Signal Clear Register CHIPSIG_CLR 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved CHIPSIG4 CHIPSIG3 CHIPSIG2 Reserved R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write...

Page 230: ...tates preemption at a system level as all transfer requests are internally broken down by the transfer controller up to DBS size byte chunks and on a system level each master s priority configured by the MSTPRI register is evaluated at burst size boundaries The DBS value can significantly impact the standalone throughput performance depending on the source and destination bus width frequency burst...

Page 231: ...y to select whether the host address is a word address or a byte address mode eHRPWM Time Base Clock TBCLK Synchronization Allows the software to globally synchronize all enabled eHRPWM modules to the time base clock TBCLK McASP AMUTEIN signal source control Allows selecting GPIO interrupt from different banks as source for the McASP AMUTEIN signal CFGCHIP1 provides this signal source control for ...

Page 232: ...MAC C1 RX Pulse Interrupt Dh EMAC C1 TX Pulse Interrupt Eh EMAC C1 Miscellaneous Interrupt Fh EMAC C2 RX Threshold Pulse Interrupt 10h EMAC C2 RX Pulse Interrupt 11h EMAC C2 TX Pulse Interrupt 12h EMAC C2 Miscellaneous Interrupt 13h 1Fh Reserved 26 22 CAP1SRC Selects the eCAP1 module event input 0 eCAP1 Pin input 1h McASP0 TX DMA Event 2h McASP0 RX DMA Event 3h McASP1 TX DMA Event 4h McASP1 RX DMA...

Page 233: ...Miscellaneous Interrupt 13h 1Fh Reserved 16 HPIBYTEAD HPI Byte Word Address Mode select This peripheral is not supported on the C6745 DSP 0 Host address is a word address 1 Host address is a byte address 15 HPIENA HPI Enable Bit This peripheral is not supported on the C6745 DSP 0 HPI is disabled 1 HPI is enabled 14 13 Reserved 0 Reserved Always read as 0 12 TBCLKSYNC eHRPWM Module Time Base Clock ...

Page 234: ...2h GPIO Interrupt from Bank 1 3h GPIO Interrupt from Bank 2 4h GPIO Interrupt from Bank 3 5h GPIO Interrupt from Bank 4 6h GPIO Interrupt from Bank 5 7h GPIO Interrupt from Bank 6 8h GPIO Interrupt from Bank 7 9h Fh Reserved 3 0 AMUTESEL0 Selects the source of McASP0 AMUTEIN signal The AMUTE0 signal is not supported on the C6745 DSP 0 Drive McASP0 AMUTEIN signal low 1h GPIO Interrupt from Bank 0 2...

Page 235: ...Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reserved 17 USB0PHYCLKGD Status of USB2 0 PHY 0 Clock is not present power is not good and PLL has not locked 1 Clock is present power is good and PLL has locked 16 USB0VBUSSENSE Status of USB2 0 PHY VBUS sense 0 PHY is not sensing voltage presence on the VBUS pin 1 PHY is sensing voltage presence on the VBUS pin 15 RESET USB2 0 PHY r...

Page 236: ...DM is connected to D 1 Differential data polarity are not altered USB_DP is connected to D and USB_DM is connected to D 7 USB1SUSPENDM USB1 1 suspend mode This peripheral is not supported on the C6745 DSP 0 Needs to be 0 whenever USB1 1 PHY is unpowered 1 Enable USB1 1 PHY 6 USB0PHY_PLLON Drives USB2 0 PHY allowing or preventing it from stopping the 48 MHz clock during USB SUSPEND 0 USB2 0 PHY is ...

Page 237: ...hown in Figure 10 44 and described in Table 10 48 Figure 10 44 Chip Configuration 3 Register CFGCHIP3 31 16 Reserved R 0 15 8 7 3 2 1 0 Reserved Reserved DIV4P5ENA EMA_CLKSRC EMB_CLKSRC R W FFh R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 48 Chip Configuration 3 Register CFGCHIP3 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8...

Page 238: ...FGCHIP4 31 16 Reserved R 0 15 8 7 3 2 1 0 Reserved Reserved AMUTECLR2 1 AMUTECLR1 AMUTECLR0 1 R W FFh R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 49 Chip Configuration 4 Register CFGCHIP4 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8 Reserved FFh Reserved Write the default value when modifying this register 7 3 Reserved 0 R...

Page 239: ...vised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Boot Considerations Chapter 11 SPRUH91D March 2013 Revised September 2016 Boot Considerations Topic Page 11 1 Introduction 240 ...

Page 240: ...ed into the BOOTCFG register which is part of the system configuration SYSCFG module when device reset is deasserted Boot mode selection is determined by the values of the BOOT pins The following boot modes are supported NAND Flash boot 8 bit NAND 16 bit NAND NOR Flash boot NOR Direct boot NOR Legacy boot NOR AIS boot HPI Boot this peripheral is not supported on the C6745 DSP I2C0 I2C1 Boot Master...

Page 241: ...er 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Programmable Real Time Unit Subsystem PRUSS Chapter 12 SPRUH91D March 2013 Revised September 2016 Programmable Real Time Unit Subsystem PRUSS Topic Page ...

Page 242: ...al masters to the resources inside the PRUSS The two PRUs can operate completely independently or in coordination with each other The two PRUs can also work in coordination with the device level host CPU This is determined by the nature of the program that is loaded into the two PRUs instruction memory Several different signaling mechanisms are available between the two PRUs and the device level h...

Page 243: ...re eCAP Module Chapter 13 SPRUH91D March 2013 Revised September 2016 Enhanced Capture eCAP Module The enhanced capture eCAP module is essential in systems where accurate timing of external events is important This chapter describes the eCAP module Topic Page 13 1 Introduction 244 13 2 Architecture 245 13 3 Applications 254 13 4 Registers 270 ...

Page 244: ... train signals Decoding current or voltage amplitude derived from duty cycle encoded current voltage sensors 13 1 2 Features The eCAP module includes the following features 32 bit time base counter 4 event time stamp registers each 32 bits Edge polarity selection for up to four sequenced time stamp capture events Interrupt on either of the four events Single shot capture of up to four event time s...

Page 245: ... bit time base counter 4 32 bit time stamp capture registers CAP1 CAP4 4 stage sequencer Modulo4 counter that is synchronized to external events ECAP pin rising falling edges Independent edge polarity rising falling edge selection for all 4 events Input capture signal prescaling from 2 62 One shot compare register 2 bits to freeze captures after 1 to 4 time stamp events Control for continuous time...

Page 246: ...enerator with 32 bit capabilities when it is not being used for input captures The counter operates in count up mode providing a time base for asymmetrical pulse width modulation PWM waveforms The CAP1 and CAP2 registers become the active period and compare registers respectively while CAP3 and CAP4 registers become the period and capture shadow registers respectively Figure 13 2 is a high level v...

Page 247: ...logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture events CEVT 1 4 APRD shadow 32 32 MODE SELECT ECCTL2 SYNCI_EN SYNCOSEL SWSYNC ECCTL2 CAP APWM Edge Polarity Select ECCTL1 CAPxPOL ECCTL1 EVTPS ECCTL1 CAPLDEN CTRRSTx ECCTL2 RE ARM CONT ONESHT STOP_WRAP Registers ECEINT ECFLG ECCLR ECFRC www ti com Architecture 247 SPRUH91D March 2013 Revised September ...

Page 248: ...nced Capture eCAP Module 13 2 2 1 Event Prescaler An input capture signal pulse train can be prescaled by N 2 62 in multiples of 2 or can bypass the prescaler This is useful when very high frequency signals are used as inputs Figure 13 4 shows a functional diagram and Figure 13 5 shows the operation of the prescale function Figure 13 4 Event Prescale Control 1 When a prescale value of 1 is chosen ...

Page 249: ...ng 0 1 2 3 0 and wraps around unless stopped A 2 bit stop register is used to compare the Mod4 counter output and when equal stops the Mod4 counter and inhibits further loads of the CAP1 CAP4 registers This occurs during one shot operation The continuous one shot block Figure 13 6 controls the start stop and reset zero functions of the Mod4 counter via a mono shot type of action that can be trigge...

Page 250: ...unter and Phase Control This counter Figure 13 7 provides the time base for event captures and is clocked via the system clock A phase register is provided to achieve synchronization with other counters via a hardware and software forced sync This is useful in APWM mode when a phase offset between modules is needed On any of the four event loads an option to reset the 32 bit counter is given This ...

Page 251: ... interrupt source from the eCAPn module going to the interrupt controller Seven interrupt events CEVT1 CEVT2 CEVT3 CEVT4 CNTOVF CTR PRD CTR CMP can be generated The interrupt enable register ECEINT is used to enable disable individual interrupt event sources The interrupt flag register ECFLG indicates if any interrupt event has been latched and contains the global interrupt flag bit INT An interru...

Page 252: ...et ECEINT ECFLG Latch Clear Latch Set CMPEQ ECFRC ECCLR ECCLR Clear ECFLG ECEINT Clear Latch Set ECFRC CTROVF ECFLG 0 1 0 Generate interrupt pulse when input 1 Latch Clear Set ECCLR ECAPxINT ECFLG Architecture www ti com 252 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 13 8 Interrupts...

Page 253: ...rresponding shadow registers CAP3 CAP4 This emulates immediate mode Writing to the shadow registers CAP3 CAP4 will invoke the shadow mode During initialization you must write to the active registers for both period and compare This automatically copies the initial values into the shadow values For subsequent compare updates during run time you only need to use the shadow registers Figure 13 9 PWM ...

Page 254: ...0x1 CTRRSTx bits define EC_ABS_MODE 0x0 define EC_DELTA_MODE 0x1 PRESCALE bits define EC_BYPASS 0x0 define EC_DIV1 0x0 define EC_DIV2 0x1 define EC_DIV4 0x2 define EC_DIV6 0x3 define EC_DIV8 0x4 define EC_DIV10 0x5 ECCTL2 ECAP Control Reg 2 CONT ONESHOT bit define EC_CONTINUOUS 0x0 define EC_ONESHOT 0x1 STOPVALUE bit define EC_EVENT1 0x0 define EC_EVENT2 0x1 define EC_EVENT3 0x2 define EC_EVENT4 0...

Page 255: ...e TSCTR counts up without resetting and capture events are qualified on the rising edge only this gives period and frequency information On an event the TSCTR contents time stamp is first captured then Mod4 counter is incremented to the next state When the TSCTR reaches FFFF FFFFh maximum value it wraps around to 0000 0000h not shown in Figure 13 10 if this occurs the CTROVF counter overflow flag ...

Page 256: ... ECCTL1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 13 1 Code Snippet for CAP Mode Absolute Time Rising Edge Trigger Code snippet for CAP mode Absolute Time Rising edge trigger Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fetch Time Stamp ...

Page 257: ...13 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module 13 3 2 Absolute Time Stamp Operation Rising and Falling Edge Trigger Example In Figure 13 11 the eCAP operating mode is almost the same as in the previous section except capture events are qualified as either rising or falling edge this now gives both period and duty cycle information Period1 t3 t1 Period2 t5 t3 etc Duty Cycle1 on...

Page 258: ...1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 13 2 Code Snippet for CAP Mode Absolute Time Rising and Falling Edge Trigger Code snippet for CAP mode Absolute Time Rising Falling edge triggers Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fe...

Page 259: ...unts up without resetting and Mod4 counter wraps around is used In Delta time mode TSCTR is Reset back to Zero on every valid event Here Capture events are qualified as Rising edge only On an event TSCTR contents time stamp is captured first and then TSCTR is reset to Zero The Mod4 counter then increments to the next state If TSCTR reaches FFFF FFFFh maximum value before the next event it wraps ar...

Page 260: ... ECCTL1 CTRRST4 EC_DELTA_MODE ECCTL1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 13 3 Code Snippet for CAP Mode Delta Time Rising Edge Trigger Code snippet for CAP mode Delta Time Rising edge trigger Run Time e g CEVT1 triggered ISR call Note here Time...

Page 261: ... Falling Edge Trigger Example In Figure 13 13 the eCAP operating mode is almost the same as in previous section except Capture events are qualified as either Rising or Falling edge this now gives both Period and Duty cycle information Period1 T1 T2 Period2 T3 T4 etc Duty Cycle1 on time T1 Period1 100 etc Duty Cycle1 off time T2 Period1 100 etc During initialization you must write to the active reg...

Page 262: ...ABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 13 4 Code Snippet for CAP Mode Delta Time Rising and Falling Edge Triggers Code snippet for CAP mode Delta Time Rising and Falling edge triggers Run Time e g CEVT1 triggered ISR call Note here Time stamp directly represen...

Page 263: ...e PWM Generation Independent Channel s Example In this example the eCAP module is configured to operate as a PWM generator Here a very simple single channel PWM waveform is generated from output pin APWMn The PWM polarity is active high which means that the compare value CAP2 reg is now a compare register represents the on time high level of the period Alternatively if the APWMPOL bit is configure...

Page 264: ...le i e compare value Run Time Instant 2 e g another ISR call ECAPxRegs CAP2 0x500 Set Duty cycle i e compare value 13 3 5 2 Multichannel PWM Generation with Synchronization Example Figure 13 15 takes advantage of the synchronization feature between eCAP modules Here 4 independent PWM channels are required with different frequencies but at integer multiples of each other to avoid beat frequencies H...

Page 265: ...aster APWM 1 module Time Time APRD 1 ACMP 1 0000 0000 APWM1 o p pin CTR PRD SyncOut 20 000 7 000 TSCTR FFFF FFFFh dc dc dc www ti com Applications 265 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 13 15 Multichannel PWM Example Using 4 eCAP Modules ...

Page 266: ...onization Register Bit Value CAP1 CAP1 10000 CTRPHS CTRPHS 0 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 13 8 ECAP3 Initialization for Multichannel PWM Generation with Synchronization Register Bit Value CAP1 CAP1 5000 CTRPHS CTRPHS 0 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC...

Page 267: ...Set Duty cycle i e compare value 550 ECAP4Regs CAP2 6500 Set Duty cycle i e compare value 6500 13 3 5 3 Multichannel PWM Generation with Phase Control Example In Figure 13 16 the Phase control feature of the APWM mode is used to control a 3 phase Interleaved DC DC converter topology This topology requires each phase to be off set by 120 from each other Hence if Leg 1 controlled by APWM1 is the ref...

Page 268: ...700 SYNCO pulse CTR PRD APWM1 Φ2 120 Φ3 240 CTRPHS 2 800 CTRPHS 3 400 APWM2 APWM3 TSCTR Applications www ti com 268 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 13 16 Multiphase channel Interleaved PWM Example Using 3 eCAP Modules ...

Page 269: ...00 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 13 12 ECAP3 Initialization for Multichannel PWM Generation with Phase Control Register Bit Value CAP1 CAP1 1200 CTRPHS CTRPHS 400 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC...

Page 270: ... Offset Value Register 2 Section 13 4 2 8h CAP1 Capture 1 Register 2 Section 13 4 3 Ch CAP2 Capture 2 Register 2 Section 13 4 4 10h CAP3 Capture 3 Register 2 Section 13 4 5 14h CAP4 Capture 4 Register 2 Section 13 4 6 28h ECCTL1 Capture Control Register 1 1 Section 13 4 7 2Ah ECCTL2 Capture Control Register 2 1 Section 13 4 8 2Ch ECEINT Capture Interrupt Enable Register 1 Section 13 4 9 2Eh ECFLG ...

Page 271: ...er phase value register that can be programmed for phase lag lead This register shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S W force via a control bit Used to achieve phase control synchronization with respect to other eCAP and EPWM time bases 13 4 3 Capture 1 Register CAP1 The capture 1 register CAP1 is shown in Figure 13 19 and described in Table 13 16 Figure 13 19 Captu...

Page 272: ...F FFFFh This register can be loaded written by Time Stamp i e counter value during a capture event Software may be useful for test purposes ACMP active register when used in APWM mode 13 4 5 Capture 3 Register CAP3 The capture 3 register CAP3 is shown in Figure 13 21 and described in Table 13 18 Figure 13 21 Capture 3 Register CAP3 31 0 CAP3 R W 0 LEGEND R W Read Write n value after reset Table 13...

Page 273: ...gure 13 23 and described in Table 13 20 Figure 13 23 ECAP Control Register 1 ECCTL1 15 14 13 9 8 FREE SOFT PRESCALE CAPLDEN R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 13 20 ECAP Control Register 1 ECCTL1 Field Descriptions Bit Field Value Descriptio...

Page 274: ...olute time stamp 1 Reset counter after Event 3 time stamp has been captured used in difference mode operation 4 CAP3POL Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge RE 1 Capture Event 3 triggered on a falling edge FE 3 CTRRST2 Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 absolute time stamp 1 Reset counter after Event 2 time stamp has b...

Page 275: ...APn APWMn pin operates as a capture input 1 ECAP module operates in APWM mode This mode forces the following configuration Resets TSCTR on CTR PRD event period boundary Permits shadow loading on CAP1 and 2 registers Disables loading of time stamps into CAP1 4 registers ECAPn APWMn pin operates as a APWM output 8 SWSYNC Software forced Counter TSCTR Synchronizing This provides a convenient software...

Page 276: ...in one shot mode Wrap after Capture Event 2 in continuous mode 2h Stop after Capture Event 3 in one shot mode Wrap after Capture Event 3 in continuous mode 3h Stop after Capture Event 4 in one shot mode Wrap after Capture Event 4 in continuous mode Notes STOP_WRAP is compared to Mod4 counter and when equal 2 actions occur Mod4 counter is stopped frozen Capture register loads are inhibited In one s...

Page 277: ...terrupt source 6 CTR PRD Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source 1 Enable Period Equal as an Interrupt source 5 CTROVF Counter Overflow Interrupt Enable 0 Disable counter Overflow as an Interrupt source 1 Enable counter Overflow as an Interrupt source 4 CEVT4 Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source 1 Enable Captu...

Page 278: ... flag is only active in APWM mode 0 Indicates no event occurred 1 Indicates the counter TSCTR reached the period register value APRD and was reset 5 CTROVF Counter Overflow Status Flag This flag is active in CAP and APWM mode 0 Indicates no event occurred 1 Indicates the counter TSCTR has made the transition from 0xFFFFFFFF to 0x00000000 4 CEVT4 Capture Event 4 Status Flag This flag is only active...

Page 279: ...tion 6 CTR PRD Counter Equal Period Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CTR PRD flag condition 5 CTROVF Counter Overflow Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CTROVF flag condition 4 CEVT4 Capture Event 4 Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CEVT3 fl...

Page 280: ...ns Bit Field Value Description 15 8 Reserved 0 Reserved 7 CTR CMP Force Counter Equal Compare Interrupt 0 No effect Always reads back a 0 1 Writing a 1 sets the CTR CMP flag bit 6 CTR PRD Force Counter Equal Period Interrupt 0 No effect Always reads back a 0 1 Writing a 1 sets the CTR PRD flag bit 5 CTROVF Force Counter Overflow 0 No effect Always reads back a 0 1 Writing a 1 to this bit sets the ...

Page 281: ... Capture eCAP Module 13 4 13 Revision ID Register REVID The revision ID register REVID is shown in Figure 13 29 and described in Table 13 26 Figure 13 29 Revision ID Register REVID 31 0 REV R 44D2 2100h LEGEND R Read only n value after reset Table 13 26 Revision ID Register REVID Field Descriptions Bit Field Value Description 31 0 REV 44D2 2100h Revision ID ...

Page 282: ...Resolution Pulse Width Modulator eHRPWM Chapter 14 SPRUH91D March 2013 Revised September 2016 Enhanced High Resolution Pulse Width Modulator eHRPWM This chapter describes the enhanced high resolution pulse width modulator eHRPWM Topic Page 14 1 Introduction 283 14 2 Architecture 288 14 3 Applications to Power Topologies 347 14 4 Registers 371 ...

Page 283: ... this feature Each ePWM module is indicated by a numerical value starting with 1 For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx indicates any instance The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required Additionally this synchronization scheme can be extended to the capt...

Page 284: ...PWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM2INT EPWMxINT To eCAP1 TZ1 TZn to TZ1 TZn to Interrupt Controller Introduction www ti com 284 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 1 Multiple ePWM Modules ...

Page 285: ...one signals TZ1 to TZn These input signals alert the ePWM module of an external fault condition Each module on a device can be configured to either use or ignore any of the trip zone signals The trip zone signal can be configured as an asynchronous input through the GPIO peripheral See your device specific data manual to determine how many trip zone pins are available in the device Time base synch...

Page 286: ...16 Counter compare CC CMPB active 16 CTR CMPB CMPB shadow 16 CMPAHR 8 EPWMA EPWMB Dead band DB PC chopper PWM zone TZ Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 Introduction www ti com 286 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instru...

Page 287: ...No Counter Compare Control Register CMPAHR 10h 1 No Extension for HRPWM Counter Compare A Register 2 CMPA 12h 1 Yes Counter Compare A Register CMPB 14h 1 Yes Counter Compare B Register Action Qualifier Submodule Registers AQCTLA 16h 1 No Action Qualifier Control Register for Output A EPWMxA AQCTLB 18h 1 No Action Qualifier Control Register for Output B EPWMxB AQSFRC 1Ah 1 No Action Qualifier Softw...

Page 288: ...on up or down of the time base counter after a synchronization event Configure how the time base counter will behave when the device is halted by an emulator Specify the source for the synchronization output of the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Section 14 2 3 Coun...

Page 289: ...Force EPWMxA and or EPWMxB low Force EPWMxA and or EPWMxB to a high impedance state Configure EPWMxA and or EPWMxB to ignore any trip condition Configure how often the ePWM will react to each trip zone pin One shot Cycle by cycle Enable the trip zone to initiate an interrupt Bypass the trip zone module entirely Section 14 2 8 Event trigger ET Enable the ePWM events that will trigger an interrupt S...

Page 290: ...it define TB_SYNC_IN 0x0 define TB_CTR_ZERO 0x1 define TB_CTR_CMPB 0x2 define TB_SYNC_DISABLE 0x3 HSPCLKDIV and CLKDIV bits define TB_DIV1 0x0 define TB_DIV2 0x1 define TB_DIV4 0x2 PHSDIR bit define TB_DOWN 0x0 define TB_UP 0x1 CMPCTL Compare Control LOADAMODE and LOADBMODE bits define CC_CTR_ZERO 0x0 define CC_CTR_PRD 0x1 define CC_CTR_ZERO_PRD 0x2 define CC_LD_DISABLE 0x3 SHDWAMODE and SHDWBMODE...

Page 291: ... TZCTL Trip zone Control TZA and TZB bits define TZ_HIZ 0x0 define TZ_FORCE_HI 0x1 define TZ_FORCE_LO 0x2 define TZ_NONE 0x3 ETSEL Event trigger Select INTSEL bit define ET_CTR_ZERO 0x1 define ET_CTR_PRD 0x2 define ET_CTRU_CMPA 0x4 define ET_CTRD_CMPA 0x5 define ET_CTRU_CMPB 0x6 define ET_CTRD_CMPB 0x7 ETPS Event trigger Prescale INTPRD bit define ET_DISABLE 0x0 define ET_1ST 0x1 define ET_2ND 0x2...

Page 292: ...ion logic allows the time base of multiple ePWM modules to work together as a single system Figure 14 4 illustrates the time base module s place within the ePWM Figure 14 4 Time Base Submodule Block Diagram 14 2 3 1 Purpose of the Time Base Submodule You can configure the time base submodule for the following Specify the ePWM time base counter TBCNT frequency or period to control how often events ...

Page 293: ... used to control and monitor the time base submodule 1 This register is available only on ePWM instances that include the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved See your device specific data manual to determine which ePWM instances include this feature Table 14 3 Time Base Submodule Registers Acronym Register Description Address Offs...

Page 294: ...ut logic CTR_dir Time base counter direction Indicates the current direction of the ePWM s time base counter This signal is high when the counter is increasing and low when it is decreasing CTR_max Time base counter equal max value TBCNT FFFFh Generated event when the TBCNT value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled versi...

Page 295: ...egister The shadow register buffers or provides a temporary holding location for the active register It has no direct effect on any control hardware At a strategic point in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period regis...

Page 296: ...solution Pulse Width Modulator eHRPWM 14 2 3 3 2 Time Base Counter Synchronization A time base synchronization scheme connects all of the ePWM modules on a device Each ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ...

Page 297: ...BCTL PHSEN bit configures the ePWM to ignore the synchronization input pulse The synchronization pulse can still be allowed to flow through to the EPWMxSYNCO and be used to synchronize other ePWM modules In this way you can set up a master time base for example ePWM1 and downstream modules ePWM2 ePWMx may elect to run in synchronization with the master 14 2 3 4 Phase Locking the Time Base Clocks o...

Page 298: ...alue TBPRD value Architecture www ti com 298 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 8 Time Base Up Count Mode Waveforms ...

Page 299: ...CTR 0 CNT_max CTR PRD www ti com Architecture 299 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 9 Time Base Down Count Mode Waveforms Figure 14 10 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down on Synchronization Event ...

Page 300: ...PRD Architecture www ti com 300 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 11 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up on Synchronization Event ...

Page 301: ...B CTR 0 EPWMxINT EPWMxA EPWMxB TZ1 to TZn CTR CMPA Time Base TB CTR PRD CTR 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM chopper PC Event Trigger and Interrupt ET Trip Zone TZ GPIO MUX Interrupt controller Interrupt controller www ti com Architecture 301 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resol...

Page 302: ...bmodule Table 14 5 lists the registers used to control and monitor the counter compare submodule Table 14 6 lists the key signals associated with the counter compare submodule 1 This register is available only on ePWM modules with the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved Refer to the device specific data manual to determine which e...

Page 303: ...ich register is written to or read from is determined by the CMPCTL SHDWAMODE and CMPCTL SHDWBMODE bits These bits enable and disable the CMPA shadow register and CMPB shadow register respectively The behavior of the two load modes is described below Shadow Mode The shadow mode for the CMPA is enabled by clearing the CMPCTL SHDWAMODE bit and the shadow register for CMPB is enabled by clearing the ...

Page 304: ...umentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 14 Counter Compare Event Waveforms in Up Count Mode NOTE An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCNT count sequence This can lead to a compare event being skipped This skipping is considered normal operation and must be taken...

Page 305: ...ecture 305 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 16 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 0 Count Down on Synchronization Event Figure 14 17 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 1 Count Up on Synchronization E...

Page 306: ...alifier Submodule 14 2 5 1 Purpose of the Action Qualifier Submodule The action qualifier submodule is responsible for the following Qualifying and generating actions set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCNT TBPRD CTR 0 Time base counter equal to zero TBCNT 0000h CTR CMPA Time base counter equal to the counter compare A register TBCNT CMPA ...

Page 307: ... zero TBCNT 0000h CTR CMPA Time base counter equal to the counter compare A TBCNT CMPA CTR CMPB Time base counter equal to the counter compare B TBCNT CMPB Software forced event Asynchronous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC The action qualifier submodule controls how the two outputs EPWMxA ...

Page 308: ... a given output For example both CTR CMPA and CTR CMPB can operate on output EPWMxA All qualifier actions are configured via the control registers found at the end of this section For clarity the drawings in this chapter use a set of symbolic actions These symbols are summarized in Figure 14 20 Each symbol represents an action as a marker in time Some actions are fixed in time zero and period whil...

Page 309: ...if TBCNT is Decrementing TBCNT TBPRD down to TBCNT 1 1 Highest Software forced event Software forced event 2 Counter equals CMPB on up count CBU Counter equals CMPB on down count CBD 3 Counter equals CMPA on up count CAU Counter equals CMPA on down count CAD 4 Counter equals zero Counter equals period TBPRD 5 Counter equals CMPB on down count CBD 1 Counter equals CMPB on up count CBU 1 6 Lowest Co...

Page 310: ...ompare register value In a running system the active compare registers CMPA and CMPB are typically updated from their respective shadow registers once every period The user specifies when the update will take place either when the time base counter reaches zero or when the time base counter reaches period There are some cases when the action based on the new value can be delayed by one period or t...

Page 311: ...ieved by using equal compare matches on the up count and down count portions of the waveform In the example shown CMPA is used to make the comparison When the counter is incrementing the CMPA match will pull the PWM output high Likewise when the counter is decrementing the compare match will pull the PWM signal low When CMPA 0 the PWM signal is low for the entire period giving the 0 duty waveform ...

Page 312: ...ut signals from ePWMx Up Down means Count up and down mode Up means up count mode and Dwn means down count mode Sym Symmetric Asym Asymmetric Table 14 13 and Table 14 14 contains initialization and runtime register configurations for the waveforms in Figure 14 22 Figure 14 22 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High 1 PWM period TBPRD 1 TTBCLK...

Page 313: ...nter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA ZRO AQ_SET CAU AQ_CLEAR AQCTLB ...

Page 314: ... Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 1 PWM period TBPRD 1 TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB 4 The Do Nothing actions X are shown for completenes...

Page 315: ...nter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA PRD AQ_CLEAR CAU AQ_SET AQCTLB ...

Page 316: ... Table 14 18 contains initialization and runtime register configurations for the waveforms Figure 14 24 Use the code in Example 14 1 to define the headers Figure 14 24 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 1 PWM frequency 1 TBPRD 1 TTBCLK 2 Pulse can be placed anywhere within the PWM cycle 0000h TBPRD 3 High time duty proportional to CMPB CMPA 4 EPWMxB ...

Page 317: ...CNT 0 Clear TB counter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 200 C8h Compare A 200 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CB...

Page 318: ...er configurations for the waveforms in Figure 14 25 Use the code in Example 14 1 to define the headers Figure 14 25 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 1 PWM period 2 x TBPRD TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by ...

Page 319: ...r TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 400 190h Compare A 400 TBCLK counts CMPB CMPB 500 1F4h Compare B 500 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTL...

Page 320: ... 14 1 to define the headers Figure 14 26 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Complementary 1 PWM period 2 TBPRD TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low i e low time duty proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active high i e high time duty proportional to CMPB 4 Outputs EPWMx can d...

Page 321: ...r TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTL...

Page 322: ... 14 1 to define the headers Figure 14 27 Up Down Count Dual Edge Asymmetric Waveform With Independent Modulation on EPWMxA Active Low 1 PWM period 2 TBPRD TBCLK 2 Rising edge and falling edge can be asymmetrically positioned within a PWM cycle This allows for pulse placement techniques 3 Duty modulation for EPWMxA is set by CMPA and CMPB 4 Low time duty for EPWMxA is proportional to CMPA CMPB 5 To...

Page 323: ...lear TB counter TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 250 FAh Compare A 250 TBCLK counts CMPB CMPB 450 1C2h Compare B 450 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CBD A...

Page 324: ... edge placement using both the CMPA and CMPB resources of the ePWM module However if the more classical edge delay based dead band with polarity control is required then the dead band generator submodule should be used The key functions of the dead band generator submodule are Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single EPWMxA input Programming s...

Page 325: ...ll be referred to as EPWMxA In and EPWMxB In Using the DBCTL IN_MODE control bits the signal source for each delay falling edge or rising edge can be selected EPWMxA In is the source for both falling edge and rising edge delay This is the default mode EPWMxA In is the source for falling edge delay EPWMxB In is the source for rising edge delay EPWMxA In is the source for rising edge delay EPWMxB In...

Page 326: ...ate drivers The waveforms for these typical cases are shown in Figure 14 30 Note that to generate equivalent waveforms to Figure 14 30 configure the action qualifier submodule to generate the signal as shown for EPWMxA Mode 6 Bypass rising edge delay and Mode 7 Bypass falling edge delay Finally the last two entries in Table 14 26 show combinations where either the falling edge delay FED or rising ...

Page 327: ...s waveforms for typical cases where 0 duty 100 Figure 14 30 Dead Band Waveforms for Typical Cases 0 Duty 100 The dead band submodule supports independent values for rising edge RED and falling edge FED delays The amount of delay is programmed using the DBRED and DBFED registers These are 10 bit registers and their value represents the number of time base clock TBCLK periods a signal edge is delaye...

Page 328: ...module The PWM chopper submodule allows a high frequency carrier signal to modulate the PWM waveform generated by the action qualifier and dead band submodules This capability is important if you need pulse transformer based gate drivers to control the power switching elements Figure 14 31 PWM Chopper Submodule 14 2 7 1 Purpose of the PWM Chopper Submodule The key functions of the PWM chopper subm...

Page 329: ...4 2 7 3 Operational Highlights for the PWM Chopper Submodule Figure 14 32 shows the operational details of the PWM chopper submodule The carrier clock is derived from SYSCLKOUT Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL register The one shot block is a feature that provides a high energy first pulse to ensure hard and fast power switch turn on while t...

Page 330: ... not shown Details of the one shot and duty cycle control are discussed in the following sections Figure 14 33 Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only 14 2 7 4 1 One Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values The width or period of the first pulse is given by T1stpulse TSYSCLKOUT 8 OSHTWTH Where TSYSCLKOUT is the p...

Page 331: ...er and associated circuitry Saturation is one such consideration To assist the gate drive designer the duty cycles of the second and subsequent pulses have been made programmable These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmable duty cycle allows a design to be tuned or optimized via software ...

Page 332: ... indicates external fault or trip conditions and the ePWM outputs can be programmed to respond accordingly when faults occur See your device specific data manual to determine the number of trip zone pins available for the device Figure 14 36 Trip Zone Submodule 14 2 8 1 Purpose of the Trip Zone Submodule The key functions of the trip zone submodule are Trip inputs TZ1 to TZn can be flexibly mapped...

Page 333: ...a valid event present on the TZn inputs The TZ n input can be individually configured to provide either a cycle by cycle or one shot trip event for a ePWM module The configuration is determined by the TZSEL CBCn and TZSEL OSHTn bits where n corresponds to the trip pin respectively Cycle by Cycle CBC When a cycle by cycle trip event occurs the action specified in the TZCTL register is carried out i...

Page 334: ...ent Configure the ePWM2 registers as follows TZSEL OSHT1 1 enables TZ as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state Configure the ePWM1 registers as follows T...

Page 335: ...C1 to CBCn TZCLR OST TZFRC OSHT Sync Trip logic Trip Trip CBC trip event OSHT trip event EPWMxA EPWMxB EPWMxA EPWMxB TZCTL TZB TZCTL TZA Async Trip Set Clear TZFLG CBC TZCLR CBC Set Clear TZFLG OST TZn TZ1 TZSEL OSHT1 to OSHTn TZn www ti com Architecture 335 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Res...

Page 336: ...o the CPU Figure 14 39 Event Trigger Submodule 14 2 9 1 Purpose of the Event Trigger Submodule The key functions of the event trigger submodule are Receives event inputs generated by the time base and counter compare submodules Uses the time base direction information for up down event qualification Uses prescaling logic to issue interrupt requests at Every event Every second event Every third eve...

Page 337: ... 2 9 3 Operational Overview of the Event Trigger Submodule The following sections describe the event trigger submodule s operational highlights Each ePWM module has one interrupt request line connected to the interrupt controller as shown in Figure 14 40 Figure 14 40 Event Trigger Submodule Inter Connectivity to Interrupt Controller The event trigger submodule monitors various event conditions the...

Page 338: ...PA when the timer is decrementing Time base counter equal to the compare B register CMPB when the timer is incrementing Time base counter equal to the compare B register CMPB when the timer is decrementing The number of events that have occurred can be read from the interrupt event counter ETPS INTCNT register bits That is when the specified event occurs the ETPS INTCNT bits are incremented until ...

Page 339: ...G INT ETSEL INTSEL 000 001 010 011 100 101 111 101 0 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB CTR 0 CTR PRD www ti com Architecture 339 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 42 Event Trigger Interrupt Generator ...

Page 340: ... Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 Architecture www ti com 340 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM 14 2 10 High Resolution PWM HRPWM Submodule ...

Page 341: ...effective resolution for conventionally generated PWM is a function of PWM frequency or period and system clock frequency Figure 14 44 Resolution Calculations for Conventionally Generated PWM If the required PWM operating frequency does not offer sufficient resolution in PWM mode you may want to consider HRPWM As an example of improved performance offered by HRPWM Table 14 31 shows resolution in b...

Page 342: ...system clock and edge position in terms of MEP steps which are controlled via an 8 bit field in the Compare A extension register CMPAHR Figure 14 45 Operating Logic Using MEP A For MEP range and rounding adjustment To generate an HRPWM waveform configure the TBM CCM and AQM registers as you would to generate a conventional PWM of a given frequency and polarity The HRPWM works together with the TBM...

Page 343: ... valid only when operating from the CMPAHR register and should be chosen to be the same as the regular load option for the CMPA register If TBPHSHR is used then this option has no effect 14 2 10 5 Operational Highlights for the High Resolution PWM Submodule The MEP logic is capable of placing an edge in one of 255 8 bits discrete time steps each of which has a time resolution on the order of 150 p...

Page 344: ...s is equivalent to an edge position of 320 ns instead of the desired 324 ns This data is shown in Table 14 34 By utilizing the MEP you can achieve an edge position much closer to the desired point of 324 ns Table 14 34 shows that in addition to the CMPA value 22 steps of the MEP CMPAHR register will position the edge at 323 96 ns resulting in almost zero error In this example it is assumed that th...

Page 345: ... in ns Furthermore it makes the code more transportable across multiple converter types running different PWM frequencies To implement the mapping scheme a two step scaling procedure is required Assumptions for this example System clock SYSCLKOUT 10 ns 100 MHz PWM frequency 1 25 MHz 1 800 ns Required PWM duty cycle PWMDuty 0 405 40 5 PWM period in terms of coarse steps PWMperiod 800 ns 10 ns 80 Nu...

Page 346: ...s not available all the way down to 0 duty cycle Although for the first 3 or 6 cycles the HRPWM capabilities are not available regular PWM duty control is still fully operational down to 0 duty In most applications this should not be an issue as the controller regulation point is usually not designed to be close to 0 duty cycle Figure 14 47 Low Duty Cycle Range Limitation Example When PWM Frequenc...

Page 347: ...tandalone module or to operate in synchronization with other identical ePWM modules 14 3 1 Overview of Multiple Modules Previously in this user s guide all discussions have described the operation of a single module To facilitate the understanding of multiple modules working together in a system the ePWM module described in reference is represented by the more simplified block diagram shown in Fig...

Page 348: ...PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled Options for SyncOut Sync flow through SyncOut connected to SyncIn Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a s...

Page 349: ...ulator eHRPWM 14 3 3 Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck A single ePWM module configured as a master can control two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated for each converter stage Figure 14 51 shows fo...

Page 350: ...errupt I P I P I P I Applications to Power Topologies www ti com 350 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 52 Buck Waveforms for Figure 14 51 Note Only three bucks shown here ...

Page 351: ...AQ_SET Table 14 36 EPWM2 Initialization for Figure 14 52 Register Bit Value Comments TBPRD TBPRD 1400 578h Period 1401 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA P...

Page 352: ...ion for Example in Figure 14 52 Run Time Note Example execution of one run time instance EPwm1Regs CMPA half CMPA 700 adjust duty for output EPWM1A EPwm2Regs CMPA half CMPA 700 adjust duty for output EPWM2A EPwm3Regs CMPA half CMPA 500 adjust duty for output EPWM3A 14 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement ePWM module 2 can be configured ...

Page 353: ...A CA CA CA CB CB CB CB www ti com Applications to Power Topologies 353 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 54 Buck Waveforms for Figure 14 53 Note FPWM2 FPWM1 ...

Page 354: ...CTLB CBU AQ_SET Set actions for EPWM1B CBD AQ_CLEAR Table 14 39 EPWM2 Initialization for Figure 14 53 Register Bit Value Comments TBPRD TBPRD 600 258h Period 1200 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO...

Page 355: ...control of multiple switching elements can also be addressed with these same ePWM modules It is possible to control a Half H bridge stage with a single ePWM module This control can be extended to multiple stages Figure 14 55 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencies of stage 1 Figure 14 56 shows the waveforms generated by the...

Page 356: ...CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA Applications to Power Topologies www ti com 356 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 56 Half H Bridge Waveforms for Figure 14 55 Note FPWM2 FPWM1 ...

Page 357: ...CTLB ZRO AQ_CLEAR Set actions for EPWM1B CAD AQ_SET Table 14 41 EPWM2 Initialization for Figure 14 55 Register Bit Value Comments TBPRD TBPRD 600 258h Period 1200 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO...

Page 358: ...h Modulator eHRPWM 14 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM The idea of multiple modules controlling a single power stage can be extended to the 3 phase Inverter case In such a case six switching elements can be controlled using three PWM modules one for each leg of the inverter Each leg must switch at the same frequency and all legs must be synchronized A master two slave...

Page 359: ...CA CA CA CA CA CA CA CA CA CA www ti com Applications to Power Topologies 359 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 58 3 Phase Inverter Waveforms for Figure 14 57 Only One Inverter Shown ...

Page 360: ..._CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM1A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Table 14 43 EPWM2 Initialization for Figure 14 57 Register Bit Value Comments TBPRD TBPRD 800 320h Period 1600 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE...

Page 361: ...HADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Example 14 6 Code Snippet for Configur...

Page 362: ...BPHS multiple PWM modules can address another class of power topologies that rely on phase relationship between legs or stages for correct operation As described in the TB module section a PWM module can be configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCNT register To illustrate this concept Figure 14 59 shows a master and slave module with a phase relation...

Page 363: ...e 1 configured as the master To work the phase relationship between adjacent modules must be F 120 This is achieved by setting the slave TBPHS registers 2 and 3 with values of 1 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slave 3 400 Both slave modules are synchronized to the master 1 module Thi...

Page 364: ...EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT Φ 0 Φ 120 Φ 120 Φ 240 Applications to Power Topologies www ti com 364 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 61 Control of a 3 Phase Interleaved DC DC Converter ...

Page 365: ... Z I A P CA CA A P CA CA A P CA CA www ti com Applications to Power Topologies 365 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 62 3 Phase Interleaved DC DC Converter Waveforms for Figure 14 61 ...

Page 366: ...n CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM1A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 20 FED 20 TBCLKs DBRED 20 RED 20 TBCLKs Table 14 46 EPWM2 Initialization for Figure 14 61 Register Bit Value Comments TBPRD TBPRD 450 1C2h Period 900 TBCLK counts TBPHS TBPHS 300 Phase 300 900 360 120 TBCTL CTRMODE TB_UPDOWN PHSEN TB...

Page 367: ..._SYNC_IN Sync flow through PHSDIR TB_UP Count UP on sync CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 20 FED 20 TBCLKs DBRED 20 RED 20 TBCLKs Example 14 7 Code Snippet...

Page 368: ...ly change the phase value on a cycle by cycle basis This feature lends itself to controlling a class of power topologies known as phase shifted full bridge or zero voltage switched full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship between legs Such a system can be implemented by allocating the resource...

Page 369: ...ransition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA www ti com Applications to Power Topologies 369 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 14 64 ZVS Full H Bridge Waveforms ...

Page 370: ...D 70 TBCLKs Table 14 49 EPWM2 Initialization for Figure 14 63 Register Bit Value Comments TBPRD TBPRD 1200 4B0h Period 1201 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UP PHSEN TB_ENABLE Slave module PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPA CMPA 600 258h Set 50 duty for EPWM2A CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on C...

Page 371: ...able 14 51 should be considered as reserved locations and the register contents should not be modified 1 This register is only available on ePWM instances that include the high resolution PWM HRPWM extension otherwise this location is reserved See your device specific data manual to determine which instances include the HRPWM Table 14 51 Time Base Submodule Registers Offset Acronym Register Descri...

Page 372: ...counter before the synchronization event In the up count and down count modes this bit is ignored 0 Count down after the synchronization event 1 Count up after the synchronization event 12 10 CLKDIV 0 7h Time base Clock Prescale Bits These bits determine part of the time base clock prescale value TBCLK SYSCLKOUT HSPCLKDIV CLKDIV 0 1 default on reset 1h 2 2h 4 3h 8 4h 16 5h 32 6h 64 7h 128 9 7 HSPC...

Page 373: ...ows 0 Up count mode 1h Down count mode 2h Up down count mode 3h Stop freeze counter operation default on reset 14 4 1 2 Time Base Status Register TBSTS The time base status register TBSTS is shown in Figure 14 66 and described in Table 14 53 Figure 14 66 Time Base Status Register TBSTS 15 3 2 1 0 Reserved CTRMAX SYNCI CTRDIR R 0 R W1C 0 R W1C 0 R 1 LEGEND R W Read Write R W1C Read Write 1 to clear...

Page 374: ...e If TBCTL PHSEN 1 then the time base counter TBCNT will be loaded with the phase TBPHS when a synchronization event occurs The synchronization event can be initiated by the input synchronization signal EPWMxSYNCI or by a software forced synchronization 14 4 1 4 Time Base Counter Register TBCNT The time base counter register TBCNT is shown in Figure 14 68 and described in Table 14 55 Figure 14 68 ...

Page 375: ...er equals zero If TBCTL PRDLD 1 then the shadow is disabled and any write or read will go directly to the active register that is the register actively controlling the hardware The active and shadow registers share the same memory map address 14 4 2 Counter Compare Submodule Registers Table 14 57 lists the memory mapped registers for the counter compare submodule See your device specific data manu...

Page 376: ...ce a load strobe occurs 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value 7 Reserved 0 Reserved 6 SHDWBMODE Counter compare B CMPB Register Operating Mode 0 Shadow mode Operates as a double buffer All writes via the CPU access the shadow register 1 Immediate mode Only the active compare B register is used All writes and rea...

Page 377: ...can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include Do nothing the event is ignored Clear Pull the EPWMxA and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled ...

Page 378: ...f this register is enabled and disabled by the CMPCTL SHDWBMODE bit By default this register is shadowed If CMPCTL SHDWBMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADBMODE bit field determines which event will load the active register from the shadow register Before a write the CMPCTL SHDWBFULL bit can be read to de...

Page 379: ... output high 3h Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 7 6 CAD 0 3h Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxA output low 2h Set force EPWMxA output high 3h Toggle EPWMxA output low output signal will be forced high and a high signal will be force...

Page 380: ...ut high 3h Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 7 6 CAD 0 3h Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxB output low 2h Set force EPWMxB output high 3h Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low...

Page 381: ... immediately the active register is directly accessed by the CPU and is not loaded from the shadow register 5 OTSFB One Time Software Forced Event on Output B 0 Writing a 0 zero has no effect Always reads back a 0 This bit is auto cleared once a write to this register is complete that is a forced event is initiated This is a one shot forced event It can be overridden by another subsequent event on...

Page 382: ...s no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect 1 0 CSFA 0 3h Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register 0 Forcing disabled ...

Page 383: ...hown in Figure 14 29 This allows you to selectively invert one of the delayed signals before it is sent out of the dead band submodule The following descriptions correspond to classical upper lower switch control as found in one leg of a digital motor control inverter These assume that DBCTL OUT_MODE 1 1 and DBCTL IN_MODE 0 0 Other enhanced modes are also possible but not regarded as typical usage...

Page 384: ...r reset Table 14 68 Dead Band Generator Rising Edge Delay Register DBRED Field Descriptions Bits Name Value Description 15 10 Reserved 0 Reserved 9 0 DEL 0 3FFh Rising Edge Delay Count 10 bit counter 14 4 4 3 Dead Band Generator Falling Edge Delay Register DBFED The dead band generator falling edge delay register DBFED is shown in Figure 14 79 and described in Table 14 69 Figure 14 79 Dead Band Ge...

Page 385: ...ead only n value after reset Table 14 70 PWM Chopper Control Register PCCTL Bit Descriptions Bits Name Value Description 15 11 Reserved 0 Reserved 10 8 CHPDUTY 0 7h Chopping Clock Duty Cycle 0 Duty 1 8 12 5 1h Duty 2 8 25 0 2h Duty 3 8 37 5 3h Duty 4 8 50 0 4h Duty 5 8 62 5 5h Duty 6 8 75 0 6h Duty 7 8 87 5 7h Reserved 7 5 CHPFREQ 0 7h Chopping Clock Frequency 0 Divide by 1 no prescale 1h Divide b...

Page 386: ...ns are available in the device See your device specific data manual Figure 14 81 Trip Zone Select Register TZSEL 15 9 8 7 1 0 Reserved OSHTn 1 OSHT1 Reserved CBCn 1 CBC1 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 14 72 Trip Zone Submodule Select Register TZSEL Field Descriptions Bits Name Value Description 15 8 OSHTn Trip zone n TZn select One Shot OSHT trip zone enabl...

Page 387: ... 3h When a trip event occurs the following action is taken on output EPWMxA Which trip zone pins can cause an event is defined in the TZSEL register Section 14 4 6 1 0 High impedance EPWMxA High impedance state 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing no action is taken on EPWMxA 14 4 6 3 Trip Zone Enable Interrupt Register TZEINT The trip zone enable interrupt ...

Page 388: ...red 1 Indicates a trip event has occurred on a pin selected as a cycle by cycle trip source The TZFLG CBC bit will remain set until it is manually cleared by the user If the cycle by cycle trip event is still present when the CBC bit is cleared then CBC will be immediately set again The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCNT 0000...

Page 389: ...effect Always reads back a 0 1 Clears the trip interrupt flag for this ePWM module TZFLG INT NOTE No further EPWMxTZINT interrupts will be generated until the flag is cleared If the TZFLG INT bit is cleared and any of the other flag bits are set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts 14 4 6 6 Trip Zone Force Register TZFRC The trip zon...

Page 390: ...rigger Force Register Section 14 4 7 5 14 4 7 1 Event Trigger Selection Register ETSEL The event trigger selection register ETSEL is shown in Figure 14 87 and described in Table 14 79 Figure 14 87 Event Trigger Selection Register ETSEL 15 4 3 2 0 Reserved INTEN INTSEL R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 14 79 Event Trigger Selection Register ETSEL Field Desc...

Page 391: ...t has occurred 2h 2 events have occurred 3h 3 events have occurred 1 0 INTPRD 0 3h ePWM Interrupt EPWMx_INT Period Select These bits determine how many selected ETSEL INTSEL events need to occur before an interrupt is generated To be generated the interrupt must be enabled ETSEL INT 1 If the interrupt status flag is set from a previous interrupt ETFLG INT 1 then no interrupt will be generated unti...

Page 392: ...tes that an ePWMx interrupt EWPMx_INT was generated No further interrupts will be generated until the flag bit is cleared Up to one interrupt can be pending while the ETFLG INT bit is still set If an interrupt is pending it will not be generated until after the ETFLG INT bit is cleared Refer to Figure 14 42 14 4 7 4 Event Trigger Clear Register ETCLR The event trigger clear register ETCLR is shown...

Page 393: ...L register The INT flag bit will be set regardless 0 Writing 0 to this bit will be ignored Always reads back a 0 1 Generates an interrupt on EPWMxINT and set the INT flag bit This bit is used for test purposes 14 4 8 High Resolution PWM Submodule Registers Table 14 84 lists the memory mapped registers for the high resolution PWM submodule See your device specific data manual for the memory address...

Page 394: ...ister TBPHSHR Field Descriptions Bit Field Value Description 15 8 TBPHSH 0 FFh Time base phase high resolution bits 7 0 Reserved 0 Reserved 14 4 8 2 Counter Compare A High Resolution Register CMPAHR The counter compare A high resolution register CMPAHR is shown in Figure 14 93 and described in Table 14 86 Figure 14 93 Counter Compare A High Resolution Register CMPAHR 15 8 7 0 CMPAHR Reserved R W 0...

Page 395: ...TR PRD counter equal period Note Load mode selection is valid only if CTLMODE 0 has been selected You should select this event to match the selection of the CMPA load mode CMPCTL LOADMODE bits in the EPWM module as follows 0 Load on CTR 0 Time base counter equal to zero TBCNT 0000h 1h Load on CTR PRD Time base counter equal to period TBCNT TBPRD 2h Load on either CTR 0 or CTR PRD should not be use...

Page 396: ...r 2016 Enhanced Quadrature Encoder Pulse eQEP Module The enhanced quadrature encoder pulse eQEP module is used for direct interface with a linear or rotary incremental encoder to get position direction and speed information from a rotating machine for use in a high performance motion and position control system This chapter describes the eQEP Topic Page 15 1 Introduction 397 15 2 Architecture 400 ...

Page 397: ...lements that look at the disk pattern with a mechanical shift of 1 4 the pitch of a line pair between them This shift is realized with a reticle or mask that restricts the view of the photo element to the desired part of the disk lines As the disk rotates the two photo elements generate signals that are shifted 90 degrees out of phase from each other These are commonly called the quadrature QEPA a...

Page 398: ...ight 2013 2016 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 2 QEP Encoder Output Signal for Forward Reverse Movement Quadrature encoders from different manufacturers come with two forms of index pulse gated index pulse or ungated index pulse as shown in Figure 15 3 A nonstandard form of index pulse is ungated In the ungated configuration the index edges ar...

Page 399: ... the constant time between unit time events and is known in advance Estimation based on Equation 1 has an inherent accuracy limit directly related to the resolution of the position sensor and the unit time period T For example consider a 500 line per revolution quadrature encoder with a velocity calculation rate of 400 Hz When used for position the quadrature encoder gives a four fold increase in ...

Page 400: ...ock and direction signals Direction count Mode In direction count mode direction and clock signals are provided directly from the external source Some position encoders have this type of output instead of quadrature output The QEPA pin provides the clock input and the QEPB pin provides the direction input QEPI Index or Zero Marker The eQEP encoder uses an index signal to assign an absolute start p...

Page 401: ...N EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA XCLK EQEPxB XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC 32 QCLR QPOSCTL 16 32 QPOSCNT QPOSMAX QPOSINIT Interrupt Controller EQEPxINT Enhanced QEP eQEP peripheral System control registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT Data bus To CPU www ti com Architecture 401 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 201...

Page 402: ... QDECCTL SOEN QS PCSOUT EQEPxIOE EQEPxSOE EQEPxIOUT EQEPxSOUT EQEPxSIN EQEPxIIN EQEPxBIN EQEPxAIN QDECCTL SWAP QEPSTS QDF EQEPA EQEPB Architecture www ti com 402 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module 15 2 3 Quadrature Decoder Unit QDU Figure 15 5 shows a functional bl...

Page 403: ...decoding and clock generation from the eQEP input signals Phase Error Flag In normal operating conditions quadrature inputs QEPA and QEPB will be 90 degrees out of phase The phase error flag PHE is set in the QFLG register when edge transition is detected simultaneously on the QEPA and QEPB signals to optionally generate interrupts State transitions marked by dashed lines in Figure 15 6 are invali...

Page 404: ...t counter Decrement counter Increment counter Decrement counter Decrement counter Increment counter Increment counter Architecture www ti com 404 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 6 Quadrature Decoder State Machine Figure 15 7 Quadrature clock and Direct...

Page 405: ...e Sync Output The eQEP peripheral includes a position compare unit that is used to generate the position compare sync signal on compare match between the position counter register QPOSCNT and the position compare register QPOSCMP This sync signal can be output using an index pin or strobe pin of the EQEP peripheral Setting the SOEN bit in the eQEP decoder control register QDECCTL enables the posit...

Page 406: ...eripheral records the occurrence of the first index marker QEPSTS FIMF and direction on the first index event marker QEPSTS FIDF in QEPSTS registers it also remembers the quadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation For example if the first reset operation occurs on the falling edge of QEPB during the forward directio...

Page 407: ...position counter overflow flag is set If the position counter is equal to ZERO then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and position counter underflow flag is set Figure 15 9 shows the position counter reset operation in this mode First index marker is defined as the quadrature edge following the first index edge The eQEP peripheral records the occur...

Page 408: ...ns 15 2 4 2 1 Index Event Latch In some applications it may not be desirable to reset the position counter on every index event and instead it may be required to operate the position counter in full 32 bit mode QEPCTL PCRM 01 and QEPCTL PCRM 10 modes In such cases the eQEP position counter can be configured to latch on the following events and direction information is recorded in the QEPSTS QDLF b...

Page 409: ...POSCNT Index interrupt index event marker QPOSILAT QEPSTS QDLF www ti com Architecture 409 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 10 Software Index Marker for 1000 line Encoder QEPCTL IEL 1 ...

Page 410: ...robe Event Latch The position counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by clearing the QEPCTL SEL bit If the QEPCTL SEL bit is set then the position counter value is latched to the QPOSSLAT register on the rising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse direction as shown in Figure 15 11 T...

Page 411: ...POSINIT register on the rising edge of strobe input If the QEPCTL SEL bits are 11 then the position counter QPOSCNT is initialized with a value in the QPOSINIT register on the rising edge of strobe input for forward direction and on the falling edge of strobe input for reverse direction The strobe event initialization interrupt flag QFLG SEI is set when the position counter is initialized with a v...

Page 412: ...position compare unit generates a position compare event on 1 to 2 transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of the eQEP position counter for reverse counting direction see Figure 15 13 Figure 15 35 shows the layout of the eQEP Position Compare Control Register QPOSCTL and Table 15 17 describes the QPOSCTL bit fields Figure 15 13 eQEP Positio...

Page 413: ...nd clear the flag by writing 1 Time measurement ΔT between unit position events will be correct if the following conditions are met No more than 65 535 counts have occurred between unit position events No direction change between unit position events The capture unit sets the eQEP overflow error flag QEPSTS COEF in the event of capture timer overflow between unit position events If a direction cha...

Page 414: ...R QEPSTS CDEF QEPCTL UTE QUTMR QUPRD SYSCLKOUT QFLG UTO UTIME 4 QCAPCTL UPPS UTOUT QEPSTS UPEVNT UPEVNT Architecture www ti com 414 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 15 eQEP Edge Capture Unit Figure 15 16 Unit Position Event for Low Speed Measurement QCA...

Page 415: ...ity Calculation Equations 4 where v k Velocity at time instant k x k Position at time instant k x k 1 Position at time instant k 1 T Fixed unit time or inverse of velocity calculation rate ΔX Incremental position movement in unit time X Fixed unit position ΔT Incremental time elapsed for unit position movement t k Time instant k t k 1 Time instant k 1 Unit time T and unit period X are configured u...

Page 416: ...on defined by sensor resolution and ZCAPCTL UPPS bits ΔT Capture Period Latch QCPRDLAT 15 2 6 eQEP Watchdog The eQEP peripheral contains a 16 bit watchdog timer that monitors the quadrature clock to indicate proper operation of the motion control system The eQEP watchdog timer is clocked from SYSCLKOUT 64 and the quadrate clock event pulse resets the watchdog timer If no quadrature clock event is ...

Page 417: ...vent so that latched values are used for velocity calculation as described in Section Section 15 2 5 Figure 15 19 eQEP Unit Time Base 15 2 8 eQEP Interrupt Structure Figure 15 20 shows how the interrupt mechanism works in the EQEP module Figure 15 20 EQEP Interrupt Generation Eleven interrupt events PCE PHE QDC WTO PCU PCO PCR PCM SEL IEL and UTO can be generated The interrupt control register QEI...

Page 418: ...R eQEP Unit Timer Register 2 0 Section 15 3 8 20h QUPRD eQEP Unit Period Register 2 0 Section 15 3 9 24h QWDTMR eQEP Watchdog Timer Register 1 0 Section 15 3 10 26h QWDPRD eQEP Watchdog Period Register 1 0 Section 15 3 11 28h QDECCTL eQEP Decoder Control Register 1 0 Section 15 3 12 2Ah QEPCTL eQEP Control Register 1 0 Section 15 3 13 2Ch QCAPCTL eQEP Capture Control Register 1 0 Section 15 3 14 2...

Page 419: ...oint 15 3 2 eQEP Position Counter Initialization Register QPOSINIT Figure 15 22 eQEP Position Counter Initialization Register QPOSINIT 31 0 QPOSINIT R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 4 eQEP Position Counter Initialization Register QPOSINIT Field Descriptions Bits Name Value Description 31 0 QPOSINIT 0 FFFF FFFFh This register contains the position value that is u...

Page 420: ...tch 15 3 5 eQEP Index Position Latch Register QPOSILAT Figure 15 25 eQEP Index Position Latch Register QPOSILAT 31 0 QPOSILAT R 0 LEGEND R W Read Write R Read only n value after reset Table 15 7 eQEP Index Position Latch Register QPOSILAT Field Descriptions Bits Name Value Description 31 0 QPOSILAT 0 FFFF FFFFh The position counter value is latched into this register on an index event as defined b...

Page 421: ...re 15 28 eQEP Unit Timer Register QUTMR 31 0 QUTMR R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 10 eQEP Unit Timer Register QUTMR Field Descriptions Bits Name Value Description 31 0 QUTMR 0 FFFF FFFFh This register acts as time base for unit time event generation When this timer value matches with unit time period value unit time event is generated 15 3 9 eQEP Unit Period R...

Page 422: ... as time base for watch dog to detect motor stalls When this timer value matches with watch dog period value watch dog timeout interrupt is generated This register is reset upon edge transition in quadrature clock indicating the motion 15 3 11 eQEP Watchdog Period Register QWDPRD Figure 15 31 eQEP Watchdog Period Register QWDPRD 15 0 QWDPRD R W 0 LEGEND R W Read Write R Read only n value after res...

Page 423: ...R 1 3h DOWN count mode for frequency measurement QCLK xCLK QDIR 0 13 SOEN Sync output enable 0 Disable position compare sync output 1 Enable position compare sync output 12 SPSEL Sync output pin selection 0 Index pin is used for sync output 1 Strobe pin is used for sync output 11 XCR External clock rate 0 2 resolution Count the rising falling edge 1 1 resolution Count the rising edge only 10 SWAP ...

Page 424: ...naffected by emulation suspend QCTMR behavior 0 Capture Timer stops immediately 1h Capture Timer counts until next unit period event 2h 3h Capture Timer is unaffected by emulation suspend 13 12 PCRM 0 3h Position counter reset mode 0 Position counter reset on an index event 1h Position counter reset on the maximum position 2h Position counter reset on the first index event 3h Position counter rese...

Page 425: ...tion counter on falling edge of the index signal 3h Software index marker Latches the position counter and quadrature direction flag on index event marker The position counter is latched to the QPOSILAT register and the direction flag is latched in the QEPSTS QDLF bit This mode is useful for software index marking 3 PHEN Quadrature position counter enable software reset 0 Reset the eQEP peripheral...

Page 426: ... Field Descriptions Bits Name Value Description 15 CEN Enable eQEP capture 0 eQEP capture unit is disabled 1 eQEP capture unit is enabled 14 7 Reserved 0 Always write as 0 6 4 CCPS 0 7h eQEP capture timer clock prescaler 0 CAPCLK SYSCLKOUT 1 1h CAPCLK SYSCLKOUT 2 2h CAPCLK SYSCLKOUT 4 3h CAPCLK SYSCLKOUT 8 4h CAPCLK SYSCLKOUT 16 5h CAPCLK SYSCLKOUT 32 6h CAPCLK SYSCLKOUT 64 7h CAPCLK SYSCLKOUT 128...

Page 427: ...ter reset Table 15 17 eQEP Position Compare Control Register QPOSCTL Field Descriptions Bit Name Value Description 15 PCSHDW Position compare shadow enable 0 Shadow disabled load Immediate 1 Shadow enabled 14 PCLOAD Position compare shadow load mode 0 Load on QPOSCNT 0 1 Load when QPOSCNT QPOSCMP 13 PCPOL Polarity of sync output 0 Active HIGH pulse output 1 Active LOW pulse output 12 PCE Position ...

Page 428: ...ndex event latch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 9 SEL Strobe event latch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 8 PCM Position compare match interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 7 PCR Position compare ready interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 6 PCO Position counter overflow interrupt en...

Page 429: ...interrupt flag 0 No interrupt generated 1 This bit is set after latching the QPOSCNT to QPOSSLAT 8 PCM eQEP compare match event interrupt flag 0 No interrupt generated 1 This bit is set on position compare match 7 PCR Position compare ready interrupt flag 0 No interrupt generated 1 This bit is set after transferring the shadow register value to the active position compare register 6 PCO Position c...

Page 430: ...P Interrupt Clear Register QCLR Field Descriptions Bit Field Value Description 15 12 Reserved 0 Always write as 0s 11 UTO Clear unit time out interrupt flag 0 No effect 1 Clears the interrupt flag 10 IEL Clear index event latch interrupt flag 0 No effect 1 Clears the interrupt flag 9 SEL Clear strobe event latch interrupt flag 0 No effect 1 Clears the interrupt flag 8 PCM Clear eQEP compare match ...

Page 431: ... Interrupt Clear Register QCLR Field Descriptions continued Bit Field Value Description 2 PHE Clear quadrature phase error interrupt flag 0 No effect 1 Clears the interrupt flag 1 PCE Clear position counter error interrupt flag 0 No effect 1 Clears the interrupt flag 0 INT Global interrupt clear flag 0 No effect 1 Clears the interrupt flag and enables further interrupts to be generated if an event...

Page 432: ...out interrupt 0 No effect 1 Force the interrupt 10 IEL Force index event latch interrupt 0 No effect 1 Force the interrupt 9 SEL Force strobe event latch interrupt 0 No effect 1 Force the interrupt 8 PCM Force position compare match interrupt 0 No effect 1 Force the interrupt 7 PCR Force position compare ready interrupt 0 No effect 1 Force the interrupt 6 PCO Force position counter overflow interr...

Page 433: ...wise rotation or reverse movement on the first index event 1 Clockwise rotation or forward movement on the first index event 5 QDF Quadrature direction flag 0 Counter clockwise rotation or reverse movement 1 Clockwise rotation or forward movement 4 QDLF eQEP direction latch flag Status of direction is latched on every index event marker 0 Counter clockwise rotation or reverse movement on index eve...

Page 434: ...QCPRD Figure 15 42 eQEP Capture Period Register QCPRD 15 0 QCPRD R W LEGEND R W Read Write R Read only n value after reset Table 15 24 eQEP Capture Period Register QCPRD Field Descriptions Bits Name Value Description 15 0 QCPRD 0 FFFFh This register holds the period count value between the last successive eQEP position events 15 3 23 eQEP Capture Timer Latch Register QCTMRLAT Figure 15 43 eQEP Cap...

Page 435: ...d only n value after reset Table 15 26 eQEP Capture Period Latch Register QCPRDLAT Field Descriptions Bits Name Value Description 15 0 QCPRDLAT 0 FFFFh eQEP capture period value can be latched into this register on two events viz unit timeout event reading the eQEP position counter 15 3 25 eQEP Revision ID Register REVID Figure 15 45 eQEP Revision ID Register REVID 31 0 REV R 44D3 1103h LEGEND R R...

Page 436: ...ety of transfer geometries and transfer sequences This chapter describes the features and operations of the EDMA3 controller Section 16 1 provides a brief overview features and terminology Section 16 2 provides the architecture details and common operations of the EDMA3 channel controller EDMA3CC and the EDMA3 transfer controller EDMA3TC Section 16 3 contains examples and common usage scenarios Se...

Page 437: ...e EDMA3 controller The EDMA3CC includes parameter RAM PaRAM channel control registers and interrupt control registers The EDMA3CC serves to prioritize incoming software requests or events from peripherals and submits transfer requests TR to the EDMA3 transfer controller The EDMA3 transfer controllers are responsible for data movement The transfer request packets TRP submitted by the EDMA3CC contai...

Page 438: ... event queues 16 event entries per event queue The EDMA3 transfer controller EDMA3TC has the following features Supports 2 dimensional transfers with independent indexes on source and destination EDMA3CC manages the 3rd dimension More then one transfer controller allows concurrent transfers Programmable priority level for each transfer controller relative to each other and other masters in the sys...

Page 439: ... main processing engine or engines on a device Typically a DSP or general purpose processor See your device specific data manual to learn more about the CPU on your system DMA channel A channel that can be triggered by external manual and chained events All DMA channels exist in the EDMA3CC Dummy set or Dummy PaRAM set A PaRAM set for which at least one of the count fields is equal to 0 and at lea...

Page 440: ...he 8 channels that can be triggered when writing to the trigger word TRWORD of a PaRAM set All QDMA channels exist in the EDMA3CC Parameter RAM PaRAM Programmable RAM that stores PaRAM sets used by DMA channels QDMA channels and linking Parameter RAM PaRAM set A 32 byte EDMA3 channel transfer definition Each parameter set consists of 8 words 4 bytes each which store the context for a DMA QDMA link...

Page 441: ...errupt processing registers for enabling disabling interrupt to be sent to the CPU interrupt status clearing registers Additionally there are Region registers Region registers allow DMA resources DMA channels and interrupts to be assigned to unique regions which can be owned by unique EDMA programmers a use model for hetero multi core devices or by unique tasks threads a use model for single core ...

Page 442: ...and is responsible for submitting a valid transfer request TR to the appropriate EDMA3TC based on the event queue to EDMA3TC association Q0 goes to TC0 and Q1 goes to TC1 etc For more details see Section 16 2 3 The EDMA3TC receives the request and is responsible for data movement as specified in the transfer request packet TRP and other necessary tasks like buffering ensuring transfers are carried...

Page 443: ... write controller Completion interface The completion interface sends completion codes to the EDMA3CC when a transfer completes and is used for generating interrupts and chained events see Section 16 2 5 for details on transfer completion reporting Figure 16 3 EDMA3 Transfer Controller EDMA3TC Block Diagram When the EDMA3TC is idle and receives its first TR the TR is received in the DMA program re...

Page 444: ...roller However the overall TR pipelining is also subject to the amount of free space in the data FIFO 16 2 2 Types of EDMA3 Transfers An EDMA3 transfer is always defined in terms of three dimensions Figure 16 4 shows the three dimensions used by EDMA3 transfers These three dimensions are defined as 1st Dimension or Array A The 1st dimension in a transfer consists of ACNT contiguous bytes 2nd Dimen...

Page 445: ...fer information for one array only Thus BCNT CCNT events are needed to completely service a PaRAM set Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 16 5 where the start address of Array N is equal to the start address of Array N 1 plus source SRCBIDX or destination DSTBIDX Frames are always separated by SRCCIDX and DSTCIDX For A synchronized transfers after the frame is exh...

Page 446: ...service a PaRAM set Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 16 6 Frames are always separated by SRCCIDX and DSTCIDX Note that for AB synchronized transfers after a TR for the frame is submitted the address update is to add SRCCIDX DSTCIDX to the beginning address of the beginning array in the frame This is different from A synchronized transfers where the address is u...

Page 447: ...ansfer parameters such as source address destination address transfer counts indexes options etc See your device specific data manual for the addresses of the PaRAM set entries The PaRAM structure supports flexible ping pong circular buffering channel chaining and autoreloading linking The first n PaRAM sets are directly mapped to the DMA channels where n is the number of DMA channels supported in...

Page 448: ...t between destination arrays within a frame 2nd dimension Valid values range from 32 768 and 32 767 14h 1 LINK Link Address The PaRAM address containing the PaRAM set to be linked copied from when the current PaRAM set is exhausted A value of FFFFh specifies a null link BCNTRLD BCNT Reload The count value used to reload BCNT when BCNT decrements to 0 TR submitted for the last array in 2nd dimensio...

Page 449: ... 0 and 65 535 Therefore the maximum number of bytes in an array is 65 535 bytes 64K 1 bytes ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3TC A transfer with ACNT equal to 0 is considered either a null or dummy transfer See Section 16 2 3 5 and Section 16 2 5 3 for details on dummy null completion conditions 16 2 3 2 5 Count for 2nd Dimension BCNT BCNT is a 16 bit unsigne...

Page 450: ...the beginning of the current array pointed to by SRC address to the beginning of the first source array in the next frame It applies to both A synchronized and AB synchronized transfers Note that when SRCCIDX is applied the current array in an A synchronized transfer is the last array in the frame Figure 16 5 while the current array in an AB synchronized transfer is the first array in the frame Fi...

Page 451: ...serviced A dummy transfer is a legal transfer of 0 bytes See Section 16 4 2 5 8 and Section 16 4 2 2 1 for more information on the SER and EMR registers respectively 16 2 3 5 Dummy Versus Null Transfer Comparison There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request A null transfer request is an error condition but a dummy transfer is a legal transfe...

Page 452: ...ate source and destination addresses between arrays based on SRCBIDX and DSTBIDX Table 16 3 shows the details of parameter updates that occur within EDMA3CC for A synchronized and AB synchronized transfers 1 In all cases no updates occur if OPT STATIC 1 for the current PaRAM set Table 16 3 Parameter Updates in EDMA3CC for Non Null Non Dummy PaRAM Set A Synchronized Transfer AB Synchronized Transfe...

Page 453: ...sociated parameter set The EDMA3CC reads the entire PaRAM set 8 words from the PaRAM set specified by LINK and writes all 8 words to the PaRAM set associated with the current channel Figure 16 8 shows an example of a linked transfer Any PaRAM set in the PaRAM can be used as a link reload parameter set however it is recommended that the PaRAM sets associated with peripheral synchronization events s...

Page 454: ...he transfer source or destination on chip memory off chip memory controllers slave peripherals support the constant addressing mode On the C674x OMAP L1x processors no peripherals memory or memory controller support constant addressing mode If the constant addressing mode is not supported the similar logical transfer can be achieved using the increment INCR mode SAM DAM 0 by appropriately programm...

Page 455: ...Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set PaRAM 0h 0h Link FFFFh 0h 0h 0h 0h 0h 0h 0h 0h 0h PaRAM set 3 Null PaRAM set 0h 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to null set OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y...

Page 456: ... 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set PaRAM CCNT X SRCCIDX X Link 4FE0h SRCBIDX X ACNT X DSTCIDX X Rsvd BCNTRLD X DSTBIDX X DST X SRC X PaRAM set 3 OPT X 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to self OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link 4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rs...

Page 457: ...in the appropriate event queue When the event reaches the head of the queue it is evaluated for submission as a transfer request to the transfer controller If the PaRAM set is valid not a NULL set then a transfer request packet TRP is submitted to the EDMA3TC and the En bit in ER is cleared At this point a new event can be safely received by the EDMA3CC If the PaRAM set associated with the channel...

Page 458: ...nsfer Request Chaining is a mechanism by which the completion of one transfer automatically sets the event for another channel When a chained completion code is detected the value of which is dictated by the transfer completion code TCC 5 0 in OPT of the PaRAM set associated with the channel it results in the corresponding bit in the chained event register CER to be set CER E TCC 1 Once a bit is s...

Page 459: ...a second QDMA event for the same QDMA channel occurs prior to the original being cleared the second QDMA event gets captured in the QDMA event miss register QEMR En 1 16 2 4 3 Comparison Between DMA and QDMA Channels The primary difference between DMA and QDMA channels is the event channel synchronization QDMA events are either autotriggered or link triggered Autotriggering allows QDMA channels to...

Page 460: ...ctates which of the 64 bits in the chain event register CER TCC and or interrupt pending register IPR TCC is set See Section 16 2 9 for details on interrupts and Section 16 2 8 for details on chaining You can also selectively program whether the transfer controller sends back completion codes on completion of the final transfer request TR of a parameter set TCCHEN or TCINTEN for all but the final ...

Page 461: ... 2 3 3 In both cases the EDMA3 channel controller does not submit the associated transfer request to the EDMA3 transfer controller s However if the set dummy null has the OPT field programmed to return completion code intermediate final interrupt chaining completion then it will set the appropriate bits in the interrupt pending register IPR or chained event register CER The internal early completi...

Page 462: ...s Table 16 5 EDMA3 DMA Channel to PaRAM Mapping PaRAM Set Number Mapping PaRAM Set 0 DMA Channel 0 Reload QDMA PaRAM Set 1 DMA Channel 1 Reload QDMA PaRAM Set 2 DMA Channel 2 Reload QDMA PaRAM Set 3 DMA Channel 3 Reload QDMA PaRAM Set 4 DMA Channel 4 Reload QDMA PaRAM Set 5 DMA Channel 5 Reload QDMA PaRAM Set 6 DMA Channel 6 Reload QDMA PaRAM Set 7 DMA Channel 7 Reload QDMA PaRAM Set 8 DMA Channel...

Page 463: ...hannels and the PaRAM sets is programmable The QDMA channel n mapping register QCHMAPn in the EDMA3CC provides programmability for the QDMA channels to be mapped to any of the PaRAM sets in the PaRAM memory map Figure 16 10 illustrates the use of QCHMAP Additionally QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel A trigger word is one of the 8 words in the PaRAM...

Page 464: ...t a single fixed location in the EDMA3CC memory map These registers control EDMA3 resource mapping and provide debug visibility and error tracking information See your device specific data manual for the EDMA3CC memory map The channel registers including DMA QDMA and interrupt registers are accessible via the global channel region address range or in the shadow n channel region address range s For...

Page 465: ...registers need to be programmed to assign ownership of DMA channels to the respective region Accesses to DMA event registers and interrupt registers via the shadow region address map are filtered through DRAE A value of 1 in the corresponding DRAE bit implies that the corresponding DMA interrupt channel is accessible a value of 0 in the corresponding DRAE bit forces writes to be discarded and retu...

Page 466: ...haining is different from linking Section 16 2 3 7 The EDMA3 link feature reloads the current channel parameter set with the linked parameter set The EDMA3 chaining feature does not modify or update any channel parameter set it provides a synchronization event to the chained channel see Section 16 2 4 1 3 for chain triggered transfer requests Chaining is achieved at either final transfer completio...

Page 467: ...DMA3 transfer completion interrupts When a completion code is returned as a result of early or normal completion the corresponding bit in IPR is set For the completion code to be returned the PaRAM set associated with the transfer must enable the transfer completion interrupt final intermediate in the channel options parameter OPT The transfer completion code TCC can be programmed to any value for...

Page 468: ...N 1 19 All but the last TR 4 All but the last TR TCINTEN 1 ITCINTEN 1 20 All TRs 5 All TRs 16 2 9 1 1 Enabling Transfer Completion Interrupts For the EDMA3 channel controller to assert a transfer completion to the external world the interrupts have to be enabled in the EDMA3CC This is in addition to setting up the TCINTEN and ITCINTEN bits in OPT of the associated PaRAM set The EDMA3 channel contr...

Page 469: ...OPT TCC 31 in its associated PaRAM set This would mean that if a transfer completion interrupt is enabled OPT TCINTEN or OPT ITCINTEN is set then based on the TCC value IPR E31 is set up on completion For proper channel operations and interrupt generation using the shadow region map you must program the DRAE that is associated with the shadow region to have read write access to both bit 0 correspo...

Page 470: ...set in IPR thereby resulting in additional interrupts It is likely that each of these bits in IPR would need different types of service therefore the ISR must check all pending interrupts and continue until all the posted interrupts are appropriately serviced Following are examples pseudo code for a CPU interrupt service routine for an EDMA3CC completion interrupt The ISR routine in Example 16 2 i...

Page 471: ...l be a unique and nonoverlapping in most cases assignment of the channels and interrupts among the different shadow regions This allows the interrupt registers IER IESR IECR IPR and ICR in the different shadow regions to functionally operate in an independent manner and nonoverlapping The above examples for the interrupt service routine is based on this assumption 16 2 9 3 Interrupt Evaluation Ope...

Page 472: ...T is set to 1 exceeding the maximum limit of 31 This also gets latched in the EDMA3CC error register CCERR Figure 16 13 illustrates the EDMA3CC error interrupt generation operation If any of the bits are set in the error registers due to any error condition the EDMA3_CC0_ERRINT always is asserted as there are no enables for masking these error events Similar to the transfer completion interrupts t...

Page 473: ...nt is processed and submitted as a transfer request packet TRP to the associated EDMA3 transfer controller A lower numbered queue has a higher dequeuing priority then a higher numbered queue For example Q0 has higher priority than Q1 if Q0 and Q1 both have at least one event entry and if both TC0 and TC1 can accept transfer requests then the event in Q0 is dequeued first and its associated PaRAM s...

Page 474: ...RTPTR field may be used to index appropriately into the 16 event entries The NUMVAL number of entries starting from STRTPTR are indicative of events still queued in the respective queue The remaining entries may be read to determine which events have already been de queued and submitted to the associated transfer controller 16 2 10 3 Queue Resource Tracking The EDMA3CC event queue includes waterma...

Page 475: ...sign for a given device The default burst size DBS for each transfer controller is configurable by the chip configuration 0 register CFGCHIP0 in the System Configuration Module The burst size for each transfer controlled can be programmed to be 16 32 or 64 bytes The default values for DBS are typically chosen for optimal performance in most intended use conditions therefore if you decide to use a ...

Page 476: ...number of destination FIFO register entries that is controlled by the DSTREGDEPTH parameter fixed in design for a given transfer controller TR pipelining refers to the ability of the TC read controller to issue read commands for a subsequent TR while the TC write controller is still performing writes for the previous TR Consider the case of 2 TRs TR0 followed by TR1 because of TR pipelining the TC...

Page 477: ... different parts of the transfer controller The SRCACTV bit indicates whether the source active set is active The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given instance The PROGBUSY bit indicates whether a valid TR is present in the DMA program set If the TRs are in progression caution must be used and you must realize that there is a chance tha...

Page 478: ...ther it is a non null and non dummy transfer request TR 4 The EDMA3CC clears the ER En or CER En ESR En QER En bit and the SER En bit as soon as it determines the TR is non null In the case of a null set the SER En bit remains set It submits the non null non dummy TR to the associated transfer controller If the TR was programmed for early completion the EDMA3CC immediately sets the interrupt pendi...

Page 479: ...ntation rules to deal with concurrent events channels transfers etc The following subsections detail various arbitration details whenever there might be occurrence of concurrent activity Figure 16 14 shows the different places EDMA3 priorities come into play 16 2 13 1 Channel Priority The DMA event register ER captures all external peripheral events connected to the EDMA3CC likewise the QDMA event...

Page 480: ...with the lower numbered higher priority queue is busy processing earlier transfer requests and the transfer controller associated with the higher numbered lower priority queue is idle then the event in the higher numbered lower priority queue will dequeue first 16 2 13 4 Master Transfer Controller Priority All master peripherals on the device have a programmable priority level When multiple master...

Page 481: ...r certain conditions For 2D transfers that is BCNT arrays of ACNT bytes if the ACNT value is less than or equal to the DBS value then the transfer controller will try to optimize the TR into a 1D transfer in order to maximize efficiency The optimization only takes place if the EDMA3TC recognizes that the 2D transfer is organized as a single dimension SAM DAM 0 increment mode SRC DST BIDX ACNT the ...

Page 482: ...ontents are undefined after device reset and you should not rely on parameters to be reset to a known state The PaRAM set must be initialized to a desired value before it is used 16 2 17 Power Management The EDMA3 EDMA3CC and EDMA3TC can be placed in reduced power modes to conserve power during periods of low activity The power management of the peripheral is controlled by the device Power and Sle...

Page 483: ...viced by the EDMA 16 3 Transfer Examples The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration The following sections provides a description and PaRAM configuration for some typical use case scenarios 16 3 1 Block Move Example The most basic transfer performed by the EDMA3 is a block move During device operation it is often necessary to transfer a bl...

Page 484: ... for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0000h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20...

Page 485: ...ixel frame of video data is stored in external memory SDRAM Each pixel is represented by a 16 bit halfword The CPU extracts a 16 12 pixel subframe of the image for processing To facilitate more efficient processing time by the CPU the EDMA3 places the subframe in internal L2 SRAM Figure 16 17 shows the transfer of a subframe from external memory to L2 Figure 16 18 shows the parameters for this tra...

Page 486: ...y with each array occupying a portion of contiguous memory spaces For these instances the EDMA3 can reorganize the data into the desired format Figure 16 19 shows the data sorting In order to determine the parameter entry values the following need to be considered ACNT Program this to be the size in bytes of an array BCNT Program this to be the number of arrays in a frame CCNT Program this to be t...

Page 487: ...t for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0010h 0004h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0004h 1000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 2...

Page 488: ... the CPU Data is always provided with some kind of synchronization event as either one element per event nonbursting or multiple elements per event bursting 16 3 4 1 Nonbursting Peripherals Nonbursting peripherals include the on chip multichannel buffered serial port McBSP and many external devices such as codecs Regardless of the peripheral the DMA channel configuration is the same The McBSP tran...

Page 489: ...nt for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 ...

Page 490: ... using AB synchronization The source address is set to the location of the video framer peripheral and the destination address is set to the start of the data buffer Since the input address is static the SRCBIDX is 0 no modification to the source address The destination is made up of arrays of contiguous linear elements therefore the DSTBIDX is set to pixel size 2 bytes ANCT is equal to the pixel ...

Page 491: ...VT for every element transmitted To service the data streams the DMA channels associated with the McBSP must be set up for 1D to 1D transfers with A synchronization Figure 16 26 shows the parameters for the parameter entries for the channel for these transfers In order to service the McBSP continuously throughout CPU operation the channels must be linked to a duplicate PaRAM set in the PaRAM After...

Page 492: ...00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Transmit Channel PaRAM Set 2 being Linked to PaRAM Set 65 Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT C...

Page 493: ... 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Reload Parameters PaRAM Set 65 for Transmit Channel Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimen...

Page 494: ...ut of the ping buffers the CPU manipulates the data in the pong buffers When both CPU and EDMA3 activity completes they switch The EDMA3 then writes over the old input data and transfers the new output data Figure 16 28 shows the ping pong scheme for this example To change the continuous operation example such that a ping pong buffering scheme is used the DMA channels need only a moderate change I...

Page 495: ...rect Memory Access EDMA3 Controller 16 3 4 4 1 Synchronization with the CPU In order to utilize the ping pong buffering technique the system must signal the CPU when to begin to access the new data set After the CPU finishes processing an input buffer ping it waits for the EDMA3 to complete before switching to the alternate pong buffer In this example both channels provide their channel numbers as...

Page 496: ...0 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0011 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Channel 2 Using PaRAM Set 2 Linked to Pong Set 65 Parameter Contents Parameter 0010 2000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for ...

Page 497: ...LD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT Figure 16 31 Ping Pong Buffering for McBSP Example Ping PaRAM a EDMA Ping Parameters for Channel 3 at Set 65 Linked to Set 64 Parameter Contents Parameter 0010 D000h Channel Options Parameter OPT 01D0 0000h Channel Source Address SRC 0080h 0001h Count for 2nd ...

Page 498: ...termediate transfer chaining ITCCHEN is for breaking up large transfers A large transfer may lock out other transfers of the same priority level for the duration of the transfer For example a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve other EDMA3 transfers on the same queue In addition this large high priority transfer may prevent the EMIF f...

Page 499: ...s event 31 ITCCHEN 1 TCC 001 1 111b and sets CER E31 1 B Transfer complete chaining synchronizes event 31 TCCHEN 1 TCC 001 1 111b and sets CER E31 1 to CPU Enable transfer complete chaining OPT TCCHEN 1 OPT TCC 001 1111b Enable intermediate transfer complete chaining OPT ITCCHEN 1 OPT TCC 001 1111b Disable intermediate transfer OPT TCINTEN 1 OPT ITCCHEN 0 complete chaining OPT TCC 001 1111b comple...

Page 500: ...s section discusses the registers of the EDMA3 controller 16 4 1 Parameter RAM PaRAM Entries Table 16 11 lists the parameter RAM PaRAM entries for the EDMA3 channel controller EDMA3CC See your device specific data manual for the memory address of these registers Table 16 11 EDMA3 Channel Controller EDMA3CC Parameter RAM PaRAM Entries Offset Acronym Parameter Section 0h OPT Channel Options Section ...

Page 501: ...ining is disabled 1 Intermediate transfer complete chaining is enabled When enabled the chained event register CER bit is set on every intermediate chained transfer completion upon completion of every intermediate TR in the PaRAM set except the final TR in the PaRAM set The bit position set in CER is the TCC value specified 22 TCCHEN Transfer complete chaining enable 0 Transfer complete chaining i...

Page 502: ...ransfer synchronization dimension 0 A synchronized Each event triggers the transfer of a single array of ACNT bytes 1 AB synchronized Each event triggers the transfer of BCNT arrays of ACNT bytes 1 DAM Destination address mode 0 Increment INCR mode Destination addressing within an array increments Destination is not a FIFO 1 Constant addressing CONST mode Destination addressing within an array wra...

Page 503: ...ddress of the source 16 4 1 3 A Count B Count Parameter A_B_CNT The A count B count parameter A_B_CNT specifies the number of bytes within the 1st dimension of a transfer and the number of arrays of length ACNT The A_B_CNT is shown in Figure 16 37 and described in Table 16 14 Figure 16 37 A Count B Count Parameter A_B_CNT 31 16 BCNT R W x 15 0 ACNT R W x LEGEND R W Read Write n value after reset x...

Page 504: ...e B index destination B index parameter SRC_DST_BIDX specifies the value 2s complement used for source address modification between each array in the 2nd dimension and the value 2s complement used for destination address modification between each array in the 2nd dimension The SRC_DST_BIDX is shown in Figure 16 39 and described in Table 16 16 Figure 16 39 Source B Index Destination B Index Paramet...

Page 505: ... 16 17 Figure 16 40 Link Address B Count Reload Parameter LINK_BCNTRLD 31 16 BCNTRLD R W x 15 0 LINK R W x LEGEND R W Read Write n value after reset x value is indeterminate after reset Table 16 17 Link Address B Count Reload Parameter LINK_BCNTRLD Field Descriptions Bit Field Value Description 31 16 BCNTRLD 0 FFFFh B count reload The count value used to reload BCNT in the A count B count paramete...

Page 506: ...ndex Destination C Index Parameter SRC_DST_CIDX Field Descriptions Bit Field Value Description 31 16 DSTCIDX 0 FFFFh Destination C index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 15 0 SRCCIDX 0 FFFFh Source C index Signed value specifying the byte address offset between frames within a block 3rd dimension V...

Page 507: ...P7 QDMA Channel 7 Mapping Register Section 16 4 2 1 3 240h DMAQNUM0 DMA Channel Queue Number Register 0 Section 16 4 2 1 4 244h DMAQNUM1 DMA Channel Queue Number Register 1 Section 16 4 2 1 4 248h DMAQNUM2 DMA Channel Queue Number Register 2 Section 16 4 2 1 4 24Ch DMAQNUM3 DMA Channel Queue Number Register 3 Section 16 4 2 1 4 260h QDMAQNUM QDMA Channel Queue Number Register Section 16 4 2 1 5 28...

Page 508: ...ar Register Section 16 4 2 6 5 1078h IEVAL Interrupt Evaluate Register Section 16 4 2 6 6 1080h QER QDMA Event Register Section 16 4 2 7 1 1084h QEER QDMA Event Enable Register Section 16 4 2 7 2 1088h QEECR QDMA Event Enable Clear Register Section 16 4 2 7 3 108Ch QEESR QDMA Event Enable Set Register Section 16 4 2 7 4 1090h QSER QDMA Secondary Event Register Section 16 4 2 7 5 1094h QSECR QDMA S...

Page 509: ...able Register 2228h EECR Event Enable Clear Register 2230h EESR Event Enable Set Register 2238h SER Secondary Event Register 2240h SECR Secondary Event Clear Register 2250h IER Interrupt Enable Register 2258h IECR Interrupt Enable Clear Register 2260h IESR Interrupt Enable Set Register 2268h IPR Interrupt Pending Register 2270h ICR Interrupt Clear Register 2278h IEVAL Interrupt Evaluate Register 2...

Page 510: ...VID Field Descriptions Bit Field Value Description 31 0 REV Peripheral identifier 4001 5300h Uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC 16 4 2 1 2 EDMA3CC Configuration Register CCCFG The EDMA3CC configuration register CCCFG provides the features resources for the EDMA3CC in a particular device The CCCFG is shown in Figure 16 44 and described in Table 16 22 Figure 16 ...

Page 511: ...try n corresponds to channel n 1 Reserved 23 22 Reserved 0 Reserved 21 20 NUM_REGN 0 3h Number of shadow regions 0 1h Reserved 2h 4 regions 3h Reserved 19 Reserved 0 Reserved 18 16 NUM_EVQUE 0 7h Number of queues number of transfer controllers 0 Reserved 1h 2 event queues 2h 2 transfer controllers 3h 7h Reserved 15 Reserved 0 Reserved 14 12 NUM_PAENTRY 0 7h Number of PaRAM sets 0 2h Reserved 3h 12...

Page 512: ...MA channel mapping registers for all QDMA channels point to the PaRAM set 0 Prior to using any QDMA channel QCHMAPn should be programmed appropriately to point to a different PaRAM set Figure 16 45 QDMA Channel n Mapping Register QCHMAPn 31 16 Reserved R 0 15 14 13 5 4 2 1 0 Reserved PAENTRY TRWORD Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 16 23 QDMA ...

Page 513: ...es which transfer controller is utilized for the data movement or which EDMA3TC receives the TR request Figure 16 46 DMA Channel Queue Number Register n DMAQNUMn 31 30 28 27 26 24 23 22 20 19 18 16 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read ...

Page 514: ... W 0 R 0 R W 0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd E3 Rsvd E2 Rsvd E1 Rsvd E0 R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 26 QDMA Channel Queue Number Register QDMAQNUM Field Descriptions Bit Field Value Description 31 0 En 0 7h QDMA queue number Contains the event queue number to be used for the corresponding QDMA channel 0 Event n is queue...

Page 515: ...R bit for a channel is also set if an event on that channel encounters a NULL entry or a NULL TR is serviced If any EMR bit is set and all errors including bits in other error registers QEMR CCERR were previously cleared the EDMA3CC generates an error interrupt See Section 16 2 9 4 for details on EDMA3CC error interrupt generation The EMR is shown in Figure 16 48 and described in Table 16 27 Figur...

Page 516: ... 16 49 and described in Table 16 28 Figure 16 49 Event Missed Clear Register EMCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W ...

Page 517: ... QEMR bit is set and all errors including bits in other error registers EMR or CCERR were previously cleared the EDMA3CC generates an error interrupt See Section 16 2 9 4 for details on EDMA3CC error interrupt generation The QEMR is shown in Figure 16 50 and described in Table 16 29 Figure 16 50 QDMA Event Missed Register QEMR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E...

Page 518: ...ars the corresponding missed event bit in QEMR writing a 0 has no effect The QEMCR is shown in Figure 16 51 and described in Table 16 30 Figure 16 51 QDMA Event Missed Clear Register QEMCR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 16 30 QDMA Event Missed Clear Register QEMCR Field Descr...

Page 519: ...ERR they can only be cleared by writing to the corresponding bits in the EDMA3CC error clear register CCERRCLR The CCERR is shown in Figure 16 52 and described in Table 16 31 Figure 16 52 EDMA3CC Error Register CCERR 31 17 16 Reserved TCCERR R 0 R 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 16 31 EDMA3CC Error Register CCERR Field Descriptions Bit...

Page 520: ...d described in Table 16 32 Figure 16 53 EDMA3CC Error Clear Register CCERRCLR 31 17 16 Reserved TCCERR W 0 W 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 16 32 EDMA3CC Error Clear Register CCERRCLR Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 TCCERR Transfer completion code error clear 0 No effect 1 Clears the TCCERR...

Page 521: ...ults in reasserting the EDMA3CC error interrupt if there are any outstanding error bits set due to subsequent error conditions Writes of 0 have no effect The EEVAL is shown in Figure 16 54 and described in Table 16 33 Figure 16 54 Error Evaluate Register EEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 R W 0 W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 16 33...

Page 522: ...ection 16 2 9 The DRAEm is shown in Figure 16 55 and described in Table 16 34 Figure 16 55 DMA Region Access Enable Register for Region m DRAEm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E1...

Page 523: ...e 16 35 Figure 16 56 QDMA Region Access Enable for Region m QRAEm 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 35 QDMA Region Access Enable for Region m QRAEm Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA region access ...

Page 524: ...E15 and Q1E0 to Q1E15 Each register details the event number ENUM and the event type ETYPE For example if the value in Q1E4 is read as 0000 004Fh this means the 4th entry in queue 1 is a manually triggered event on DMA channel 15 The QxEy is shown in Figure 16 57 and described in Table 16 36 Figure 16 57 Event Queue Entry Registers QxEy 31 16 Reserved R 0 15 8 7 6 5 4 0 Reserved ETYPE Rsvd ENUM R ...

Page 525: ...0 Threshold specified by the Qn bit in the queue watermark threshold A register QWMTHRA has not been exceeded 1 Threshold specified by the Qn bit in the queue watermark threshold A register QWMTHRA has been exceeded 23 21 Reserved 0 Reserved 20 16 WM 0 1Fh Watermark for maximum queue usage Watermark tracks the most entries that have been in queue n since reset or since the last time that the water...

Page 526: ...ription 31 13 Reserved 0 Reserved 12 8 Q1 0 1Fh Queue threshold for queue 1 value The QTHRXCD1 bit in the EDMA3CC error register CCERR and the THRXCD bit in the queue status register 1 QSTAT1 are set when the number of events in queue 1 at an instant in time visible via the NUMVAL bit in QSTAT1 equals or exceeds the value specified by Q1 0 10h The default is 16 maximum allowed 11h Disables the thr...

Page 527: ...uest active The COMPACTV field reflects the count for the number of completion requests submitted to the transfer controllers This count increments every time a TR is submitted and is programmed to report completion the TCINTEN or TCCCHEN bits in OPT in the parameter entry associated with the TR are set to 1 The counter decrements for every valid TCC received back from the transfer controllers If ...

Page 528: ...6 39 EDMA3CC Status Register CCSTAT Field Descriptions continued Bit Field Value Description 1 QEVTACTV QDMA event active 0 No enabled QDMA events are active within the EDMA3CC 1 At least one enabled QDMA event QER is active within the EDMA3CC 0 EVTACTV DMA event active 0 No enabled DMA events are active within the EDMA3CC 1 At least one enabled DMA event ER and EER ESR CER is active within the ED...

Page 529: ...eady set and another event is received on the same channel event then the corresponding event is latched in the event miss register EMR En provided that the event was enabled EER En 1 Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register ECR The setting of an event is a higher priority relative to clear operations via hardware or software If set and c...

Page 530: ...t is set in the event register it remains set until EDMA3CC submits a transfer request for that event or the CPU clears the event by setting the corresponding bit in ECR The ECR is shown in Figure 16 62 and described in Table 16 41 Figure 16 62 Event Clear Register ECR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W ...

Page 531: ...ons via hardware If set and clear conditions occur concurrently the set condition wins If the event was previously set then EMR would be set since an event is lost If the event was previously clear then the event remains set and is prioritized for submission to the event queues Manually triggered transfers via writes to ESR allow the CPU to submit DMA requests in the system these are relevant for ...

Page 532: ...gister are cleared when the corresponding events are prioritized and serviced If the En bit is already set and another chaining completion code is return for the same event then the corresponding event is latched in the event missed register EMR En 1 The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrently the set conditi...

Page 533: ...y set in the event register enables the EDMA3CC to process the already set event like any other new event The EER settings do not have any effect on chained events CER En 1 and manually set events ESR En 1 The EER is shown in Figure 16 65 and described in Table 16 44 Figure 16 65 Event Enable Register EER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E...

Page 534: ...lear Register EECR Field Descriptions Bit Field Value Description 31 0 En Event enable clear for events 0 31 0 No effect 1 Event is disabled Corresponding bit in the event enable register EER is cleared En 0 16 4 2 5 7 Event Enable Set Register EESR The event enable register EER cannot be modified by directly writing to it The intent is to ease the software burden for the case where multiple tasks...

Page 535: ...E23 E22 E21 E20 E19 E18 E17 E16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 16 47 Secondary Event Register SER Field Descriptions Bit Field Value Description 31 0 En Secondary eve...

Page 536: ...nels The IER cannot be written to directly To set any interrupt bit in IER a 1 must be written to the corresponding interrupt bit in the interrupt enable set registers IESR Similarly to clear any interrupt bit in IER a 1 must be written to the corresponding interrupt bit in the interrupt enable clear register IECR The IER is shown in Figure 16 70 and described in Table 16 49 Figure 16 70 Interrupt...

Page 537: ...able Clear Register IECR Field Descriptions Bit Field Value Description 31 0 En Interrupt enable clear for channels 0 31 0 No effect 1 Corresponding bit in the interrupt enable register IER is cleared In 0 16 4 2 6 3 Interrupt Enable Set Register IESR The interrupt enable set register IESR is used to enable interrupts Writes of 1 to the bits in IESR set the corresponding interrupt bits in the inte...

Page 538: ...er IPR In if n 0 to 31 Note that once a bit is set in the interrupt pending registers it remains set it is your responsibility to clear these bits The bits set in IPR are cleared by writing a 1 to the corresponding bits in the interrupt clear registers ICR The IPR is shown in Figure 16 73 and described in Table 16 52 Figure 16 73 Interrupt Pending Register IPR 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 539: ...upts The ICR is shown in Figure 16 74 and described in Table 16 53 Figure 16 74 Interrupt Clear Register ICR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 W 0 W 0 W 0 W 0 W 0 W 0...

Page 540: ...cribed in Table 16 54 Figure 16 75 Interrupt Evaluate Register IEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 16 54 Interrupt Evaluate Register IEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempt...

Page 541: ...ched only if the QDMA event enable register QEER channel n bit is also enabled QEER En 1 Once a bit is set in QER then the corresponding QDMA event auto trigger is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer controllers The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrent...

Page 542: ...clear register QEECR it will disable the corresponding QDMA channel The QDMA event register will not latch any event for a QDMA channel if it is not enabled via QEER The QEER is shown in Figure 16 77 and described in Table 16 56 Figure 16 77 QDMA Event Enable Register QEER 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read onl...

Page 543: ... Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA event enable clear for channels 0 7 0 No effect 1 QDMA event is disabled Corresponding bit in the QDMA event enable register QEER is cleared En 0 16 4 2 7 4 QDMA Event Enable Set Register QEESR The QDMA event enable register QEER cannot be modified by directly writing to the register in order to ease the software burden when multiple ta...

Page 544: ...e software using QSECR needs to clear the QSER bits for the EDMA3CC to evaluate subsequent QDMA events on the channel Based on whether the associated TR is valid or it is a null or dummy TR the implications on the state of QSER and the required user action in order to submit another QDMA transfer might be different The QSER is shown in Figure 16 80 and described in Table 16 59 Figure 16 80 QDMA Se...

Page 545: ...y event clear register SECR operation which only clears the secondary event register SER bits and does not affect the event registers The QSECR is shown in Figure 16 81 and described in Table 16 60 Figure 16 81 QDMA Secondary Event Clear Register QSECR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n valu...

Page 546: ...ection 16 4 3 6 8 260h SADSTBREF Source Active Destination Address B Reference Register Section 16 4 3 6 9 280h DFCNTRLD Destination FIFO Set Count Reload Register Section 16 4 3 6 10 284h DFSRCBREF Destination FIFO Set Source Address B Reference Register Section 16 4 3 6 11 288h DFDSTBREF Destination FIFO Set Destination Address B Reference Register Section 16 4 3 6 12 300h DFOPT0 Destination FIF...

Page 547: ... 3 6 17 3D4h DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Section 16 4 3 6 18 16 4 3 1 Revision Identification Register REVID The revision identification register REVID is a constant register that uniquely identifies the EDMA3TC and specific revision of the EDMA3TC The REVID is shown in Figure 16 82 and described in Table 16 62 Figure 16 82 Revision ID Register REVID 31 0 REV R 40...

Page 548: ...IDTH Rsvd FIFOSIZE R 0 R x R 0 R x R 0 R x LEGEND R Read only n value after reset x value is indeterminate after reset Table 16 63 EDMA3TC Configuration Register TCCFG Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 8 DREGDEPTH 0 3h Destination register FIFO depth parameterization 0 1 entry 1h 2 entry 2h 4 entry for EDMA3TC0 and EDMA3TC1 3h Reserved 7 6 Reserved 0 Reserv...

Page 549: ...ation FIFO contains 1 TR 2h Destination FIFO contains 2 TR 3h Destination FIFO contains 3 TR 4h Destination FIFO contains 4 TR Full if DSTREGDEPTH 4 If the destination register FIFO is empty then any TR written to Prog Set immediately transitions to the destination register FIFO If the destination register FIFO is not empty and not full then any TR written to Prog Set immediately transitions to th...

Page 550: ...ue after reset Table 16 65 Error Status Register ERRSTAT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR MMR address error 0 MMR address error is not detected 1 User attempted to read or write to an invalid address in configuration memory map 2 TRERR Transfer request TR error event 0 Transfer request TR error is not detected 1 Transfer request TR detected that vio...

Page 551: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 66 Error Enable Register ERREN Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR Interrupt enable for MMR address error MMRAERR 0 MMRAERR is disabled 1 MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation 2 TRERR Interrupt enable for transfer request error TRERR 0...

Page 552: ...ptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR Interrupt enable clear for the MMR address error MMRAERR bit in the error status register ERRSTAT 0 No effect 1 Clears the MMRAERR bit in the error status register ERRSTAT but does not clear the error details register ERRDET 2 TRERR Interrupt enable clear for the transfer request error TRERR bit in the error status register ERRS...

Page 553: ... 1 Transfer completion interrupt enable Contains the TCINTEN value in the channel options parameter OPT programmed by the channel controller for the read or write transaction that resulted in an error 15 14 Reserved 0 Reserved 13 8 TCC 0 3Fh Transfer complete code Contains the TCC value in the channel options parameter OPT programmed by the channel controller for the read or write transaction that...

Page 554: ...d register ERRCMD is shown in Figure 16 89 and described in Table 16 69 Figure 16 89 Error Interrupt Command Register ERRCMD 31 16 Reserved R 0 15 1 0 Reserved EVAL R 0 W 0 LEGEND R Read only W Write only n value after reset Table 16 69 Error Interrupt Command Register ERRCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 EVAL Error evaluate 0 No effect 1 EDMA3TC error l...

Page 555: ...RATE can be manipulated to slow down the access rate so that the endpoint may service requests from other masters during the inactive EDMA3TC cycles The RDRATE is shown in Figure 16 90 and described in Table 16 70 NOTE It is expected that the RDRATE value for a transfer controller is static as it is decided based on the application requirement It is not recommended to change this setting on the go...

Page 556: ...ration Module You should use the chip level registers and not QUEPRI to configure the TC priority Figure 16 91 Source Active Options Register SAOPT 31 23 22 21 20 19 18 17 16 Reserved TCCHEN Rsvd TCINTEN Reserved TCC R 0 R W 0 R 0 R W 0 R 0 R W 0 15 12 11 10 8 7 6 4 3 2 1 0 TCC Rsvd FWID Rsvd PRI 1 Reserved DAM SAM R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value...

Page 557: ...EGEND R Read only n value after reset Table 16 72 Source Active Source Address Register SASRC Field Descriptions Bit Field Value Description 31 0 SADDR 0 FFFF FFFFh Source address for program register set EDMA3TC updates value according to source addressing mode SAM bit in the source active options register SAOPT 16 4 3 6 3 Source Active Count Register SACNT The source active count register SACNT ...

Page 558: ... Field Descriptions Bit Field Value Description 31 0 DADDR 0 Always reads as 0 16 4 3 6 5 Source Active B Index Register SABIDX The source active B index register SABIDX is shown in Figure 16 95 and described in Table 16 75 Figure 16 95 Source Active B Index Register SABIDX 31 16 DSTBIDX R 0 15 0 SRCBIDX R 0 LEGEND R Read only n value after reset Table 16 75 Source Active B Index Register SABIDX F...

Page 559: ...evel used by the host to set up the parameter entry in the channel controller This field is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing Read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor ...

Page 560: ...it Field Value Description 31 16 Reserved 0 Reserved 15 0 ACNTRLD 0 FFFFh A count reload value Represents the originally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced 16 4 3 6 8 Source Active Source Address B Reference Register SASRCBREF The source active source address B reference register SASRCBREF is shown in Figure 16 98 and described in Ta...

Page 561: ...ve Destination Address B Reference Register SADSTBREF Field Descriptions Bit Field Value Description 31 0 DADDRBREF 0 Always reads as 0 16 4 3 6 10 Destination FIFO Set Count Reload Register DFCNTRLD The destination FIFO set count reload register DFCNTRLD is shown in Figure 16 100 and described in Table 16 80 Figure 16 100 Destination FIFO Set Count Reload Register DFCNTRLD 31 16 Reserved R 0 15 0...

Page 562: ...Address B Reference Register DFSRCBREF Field Descriptions Bit Field Value Description 31 0 SADDRBREF 0 Not applicable Always Read as 0 16 4 3 6 12 Destination FIFO Set Destination Address B Reference DFDSTBREF The destination FIFO set destination address B reference register DFDSTBREF is shown in Figure 16 102 and described in Table 16 82 Figure 16 102 Destination FIFO Set Destination Address B Re...

Page 563: ...Reserved 20 TCINTEN Transfer complete interrupt enable 0 Transfer complete interrupt is disabled 1 Transfer complete interrupt is enabled 19 18 Reserved 0 Reserved 17 12 TCC 0 3Fh Transfer complete code This 6 bit code is used to set the relevant bit in CER or IPR of the EDMA3CC 11 Reserved 0 Reserved 10 8 FWID 0 7h FIFO width Applies if either SAM or DAM is set to constant addressing mode 0 FIFO ...

Page 564: ...DR 0 Always Read as 0 16 4 3 6 15 Destination FIFO Count Register n DFCNTn The destination FIFO count register n DFCNTn is shown in Figure 16 105 and described in Table 16 85 Figure 16 105 Destination FIFO Count Register n DFCNTn 31 16 BCNT R 0 15 0 ACNT R 0 LEGEND R Read only n value after reset Table 16 85 Destination FIFO Count Register n DFCNTn Field Descriptions Bit Field Value Description 31...

Page 565: ...ddress for the destination FIFO register set When a transfer request TR is complete the final value should be the address of the last write command issued 16 4 3 6 17 Destination FIFO B Index Register n DFBIDXn The destination FIFO B index register n DFBIDXn is shown in Figure 16 107 and described in Table 16 87 Figure 16 107 Destination FIFO B Index Register n DFBIDXn 31 16 DSTBIDX R 0 15 0 SRCBI...

Page 566: ...rivilege level used by the EDMA programmer to set up the parameter entry in the channel controller This field is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing Read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level pr...

Page 567: ...inuous mode The peripheral may be set up to continuously generate infinite events for instance in case of the McBSP every time the data shifts out from DXR it generates an XEVT The parameter set may be programmed to expect only a finite number of events and to be terminated by a NULL link After the expected number of events the parameter set is reloaded with a NULL parameter set Because the periph...

Page 568: ...egion completion interrupts For example if DRAE0 E0 and DRAE1 E0 are both set then on completion of a transfer that returns a TCC 0 they will generate both shadow region 0 and 1 completion interrupts 4 While programming a non dummy parameter set ensure the CCNT is not left to zero 5 Enable the EDMA3CC error interrupt in the device controller and attach an interrupt service routine ISR to ensure th...

Page 569: ...ly enable the QDMA channel just before the write to the trigger word See Section 16 3 for parameter set field setups for different types of transfers See the sections on chaining Section 16 2 8 and interrupt completion Section 16 2 9 on how to set up final intermediate completion chaining and or interrupts 3 Interrupt setup a If working in the context of a shadow region ensure the relevant bits in...

Page 570: ...Module Chapter 17 SPRUH91D March 2013 Revised September 2016 EMAC MDIO Module This chapter provides a functional description of the Ethernet Media Access Controller EMAC and physical layer PHY device Management Data Input Output MDIO module integrated in the device Topic Page 17 1 Introduction 571 17 2 Architecture 574 17 3 Registers 617 ...

Page 571: ...o physical layer device PHY EMAC acts as DMA master to either internal or external device memory space Eight receive channels with VLAN tag discrimination for receive quality of service QOS support Eight transmit channels with round robin or fixed priority for transmit quality of service QOS support Ether Stats and 802 3 Stats statistics gathering Transmit CRC generation selectable on a per channe...

Page 572: ...uired parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the network The EMAC on this device supports 10Base T 10 Mbits sec and 100BaseTX 100 Mbits sec half duplex and full duplex mode and ...

Page 573: ... unique 6 byte address that identifies an Ethernet device on the network In an Ethernet packet a MAC address is used twice first to identify the packet s destination and second to identify the packet s sender or source An Ethernet MAC address is normally specified in hexadecimal using dashes to separate bytes For example 08h 00h 28h 32h 17h 42h The first three bytes normally designate the manufact...

Page 574: ... MAC looks for only certain multicast addresses on a network to reduce traffic load The multicast address list of acceptable packets is specified by the application Physical Layer and Media Notation To identify different Ethernet technologies a simple three field type notation is used The Physical Layer type used by the Ethernet is specified by these fields data rate in Mb s medium type maximum se...

Page 575: ...ackets without CPU intervention This EMAC RAM is also referred to as the CPPI buffer descriptor memory because it complies with the Communications Port Programming Interface CPPI v3 0 standard The packet buffer descriptors can also be placed in other on and off chip memories such as L2 and EMIF There are some tradeoffs in terms of cache performance and throughput when descriptors are placed in the...

Page 576: ...when the network is not idle in either transmit or receive The pin is deasserted when both transmit and receive are idle This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK In full duplex operation the MII_CRS pin should be held low MII_RXCLK I Receive clock MII_RXCLK The receive clock is a continuous clock that provides the timing reference for receive operations The MII_RXD MII...

Page 577: ...RMII_TXEN is synchronous to RMII_MHZ_50_CLK RMII_MHZ_50_CLK I RMII reference clock RMII_MHZ_50_CLK The reference clock is used to synchronize all RMII signals RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz RMII_RXD 1 0 I Receive data RMII_RXD The receive data pins are a collection of 2 bits of data RMRDX0 is the least significant bit LSB The signals are synchronized by RMII_MHZ_50_CLK and ...

Page 578: ...eld contains the Ethernet MAC address of the EMAC port for which the frame is intended It may be an individual or multicast including broadcast address When the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address Th...

Page 579: ...rs for the presence of signal energy coming from other ports If the port transmits the entire frame without detecting signal energy from other Ethernet devices the port is done with the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 After transmitting the jam signal the port enters an exponen...

Page 580: ...ist 1 Buffer Pointer The buffer pointer refers to the actual memory buffer that contains packet data during transmit operations or is an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that ...

Page 581: ...a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time the software application simply writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has of detecting the end of the list Therefore in the case wher...

Page 582: ...nd receive interrupts are enabled by setting the mask registers RXINTMASKSET and TXINTMASKSET 2 Global interrupts for the appropriate interrupt core registers are set in the EMAC control module CnRXEN and CnTXEN on core n 3 The CPU interrupt controller is configured to accept Cn_RX_PULSE and Cn_TX_PULSE interrupts from the EMAC control module Whether or not the interrupt is enabled the current sta...

Page 583: ...mple 17 1 Transmit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMA...

Page 584: ...alue of 000Fh indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the start of packet SO...

Page 585: ... packet the EOP flag is set and there are no more descriptors in the transmit list next descriptor pointer is NULL The software application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on E...

Page 586: ... is NULL If the pNext pointer is initially NULL and more empty buffers can be added to the pool the software application may alter this pointer to point to a newly appended descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receive channel in question and the software appl...

Page 587: ...NTROL 0x00200000u define EMAC_DSC_FLAG_OVERRUN 0x00100000u define EMAC_DSC_FLAG_CODEERROR 0x00080000u define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u 17 2 5 5 3 Buffer Offset This 16 bit field must be initialized to zero by the software application before adding the descriptor to a receive queue Whether or not this fiel...

Page 588: ...t has the EOP flag set This flag is initially cleared by the software application before adding the descriptor to the receive queue This bit is set by the EMAC on EOP descriptors 17 2 5 5 8 Ownership OWNER Flag When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software application before adding the descriptor to the receive descriptor queue Thi...

Page 589: ...ersized and was not discarded because the RXCSFEN bit was set in the RXMBPENABLE 17 2 5 5 16 Control Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE 17 2 5 5 17 Overrun Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet was abort...

Page 590: ... includes 8K bytes of internal memory CPPI buffer descriptor memory The internal memory block is essential for allowing the EMAC to operate more independently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC s internal FIFOs A descriptor...

Page 591: ... PHY devices connected to the Ethernet Media Access Controller EMAC The device supports a single PHY being connected to the EMAC at any given time The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system Once a PHY device has b...

Page 592: ...resses in order to enumerate the PHY devices in the system The module tracks whether or not a PHY on a particular address has responded and whether or not the PHY currently has a link Using this information allows the software application to quickly determine which MDIO address the PHY is using 17 2 7 1 3 Active PHY Monitoring Once a PHY candidate has been selected for use the MDIO module transpar...

Page 593: ... PHY alive status register ALIVE and MDIO PHY link status register LINK The corresponding bit for the connected PHY 0 31 is set in ALIVE if the PHY responded to the read request The corresponding bit is set in LINK if the PHY responded and also is currently linked In addition any PHY register read transactions initiated by the application software using USERACCESSn causes ALIVE to be updated The U...

Page 594: ...to the PHY and PHY register you want to write 3 The write operation to the PHY is scheduled and completed by the MDIO module Completion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 in the MDIO user command complete interrupt register USERINTRAW corresponding to USERACCESSn used If in...

Page 595: ...SL is shown in Example 17 3 USERACCESS0 is assumed Note that this implementation does not check the ACK bit in USERACCESSn on PHY register reads does not follow the procedure outlined in Section 17 2 7 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknowledging read operations It is possible that a PHY could become inactive at a ...

Page 596: ...e RMII The interface between the EMAC module and the system core is provided through the EMAC control module The EMAC consists of the following logical components The receive path includes receive DMA engine receive FIFO and MAC receiver The transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic Clock...

Page 597: ...ters registers for both transmit and receive channels 17 2 8 1 9 EMAC Interrupt Controller The interrupt controller contains the interrupt related registers and logic The 26 raw EMAC interrupts are input to this submodule and masked module interrupts are output 17 2 8 1 10 Control Registers and Logic The EMAC is controlled by a set of memory mapped registers The control logic also signals transmit...

Page 598: ...viced to recover their associated memory buffer Thus it is possible to delay servicing of the EMAC interrupt if there are real time tasks to perform Eight channels are supplied for both transmit and receive operations On transmit the eight channels represent eight independent transmit queues The EMAC can be configured to treat these channels as an equal priority round robin queue or as a set of ei...

Page 599: ...lgorithm Receive flow control does not depend on the value of the incoming frame destination address A collision is generated for any incoming packet regardless of the destination address if any EMAC enabled channel s free buffer register value is less than or equal to the channel s flow threshold value 17 2 9 1 3 2 IEEE 802 3x Based Receive Buffer Flow Control IEEE 802 3x based receive buffer flo...

Page 600: ...checking on the outgoing CRC 17 2 9 2 3 Adaptive Performance Optimization APO The EMAC incorporates adaptive performance optimization APO logic that may be enabled by setting the TXPACE bit in the MAC control register MACCONTROL Transmission pacing to enhance performance is enabled when the TXPACE bit is set Adaptive performance pacing introduces delays into the normal transmission of frames delay...

Page 601: ...s or If the new pause time value is 0 then the transmit pause timer immediately expires else The EMAC transmit pause timer immediately is set to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any...

Page 602: ...The RXCHnEN bits determine whether the given channel is enabled when set to 1 to receive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if broadcast frames are enabled or filtered If broadcast frames are enabled when set to 1 then they are copied to only a single channel...

Page 603: ...multicast broadcast promiscuous channel enable register RXMBPENABLE 17 2 10 5 Host Free Buffer Tracking The host must track free buffers for each enabled channel including unicast multicast broadcast and promiscuous if receive QOS or receive flow control is used Disabled channel free buffer values are do not cares During initialization the host should write the number of free buffers for each enab...

Page 604: ...e first three CRC bytes If the frame length is 1520 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last two bytes are the first two CRC bytes If the frame length is 1521 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last byte is the first CRC byte If the frame length is 1522 there are 1518 bytes transferred to memory The ...

Page 605: ...ed 0 1 1 1 0 Proper oversize jabber code align CRC data and control frames transferred to promiscuous channel No undersized frames are transferred 0 1 1 1 1 All nonaddress matching frames with and without errors transferred to promiscuous channel 1 X 0 0 0 Proper data frames transferred to address match channel 1 X 0 0 1 Proper undersized data frames transferred to address match channel 1 X 0 1 0 ...

Page 606: ...ame reception is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 17 6 shows how the overrun condition is handled for the middle of frame overrun Table 17 6 Middle of Frame Overrun Treatment Address Match RXCAFEN RXCEFEN Middle of Frame Overrun Tr...

Page 607: ...e transmit control register TXCONTROL Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations 17 2 11 2 Transmit Channel Teardown The host commands a transmit channel teardown by writing the channel number to the transmit teardown register TXTEARDOWN When a teardown command is issued to an enabled transmit channel the following occurs Any frame currently ...

Page 608: ...ny required buffer descriptor reads for the cell data Latency to system s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level Latency to descriptor RAM is low because RAM is local to the EMAC as it is part of the EMAC control module 17 2 13 Transfer Node Priority The device contains a chip level master priority...

Page 609: ... values Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus it is the responsibility of the software to verify that there are no pending frames to be transferred After writing a 1 to the SOFTRESET bit it may be polled to determine if the reset has occurred If a 1 is read the reset has not yet occurred if a 0 is read the...

Page 610: ...ule interrupt control registers CnRXTHRESHEN CnRXEN CnTXEN and CnMISCEN The process of mapping the EMAC interrupts to the CPU is done through the CPU interrupt controller Once the interrupt is mapped to a CPU interrupt general masking and unmasking of interrupts to control reentrancy should be done at the chip level by manipulating the interrupt core enable mask registers 17 2 15 3 MDIO Module Ini...

Page 611: ...he receive channel n free buffer count registers RXnFREEBUFFER receive channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH 7 Most device drivers open with no multicast addresses so clear the MAC address hash registers MACHASH1 and MACHASH2 to 0 8 Write the receive buffer offset register RXBUFFEROFFSET value typically ze...

Page 612: ...ed to the queue s associated transmit completion pointer in the transmit DMA state RAM The data written by the host buffer descriptor address of the last processed buffer is compared to the data in the register written by the EMAC port address of last buffer descriptor used by the EMAC If the two values are not equal which means that the EMAC has transmitted more packets than the CPU has processed...

Page 613: ...r the host may acknowledge interrupts for every packet The application software must acknowledge the EMAC control module after processing packets by writing the appropriate CnTX key to the EMAC End Of Interrupt Vector register MACEOIVECTOR See Section 17 3 3 12 for the acknowledge key values 17 2 16 1 3 Statistics Interrupt The statistics level interrupt STATPEND is issued when any statistics valu...

Page 614: ...fer count and threshold logic as does flow control but the interrupts are independently enabled from flow control The threshold interrupts are intended to give the host an indication that resources are running low for a particular channel s The applications software must acknowledge the EMAC control module after receiving threshold interrupts by writing the appropriate CnRXTHRESH key to the EMAC E...

Page 615: ...trol logic contained in the EMAC control module Section 17 2 6 3 discusses the interrupt control contained in the EMAC control module For safe interrupt processing upon entry to the ISR the software application should disable interrupts using the EMAC control module registers CnRXTHRESHEN CnRXEN CnTXEN CnMISCEN and then reenable them upon leaving the ISR If any interrupt signals are active at that...

Page 616: ... turned on reset to the peripheral is asserted and clocks to the peripheral are gated after that The registers are reset to their default value When powering up after a synchronized reset all the EMAC submodules need to be reinitialized before any data transmission can happen For more information on the use of the PSC see the Power and Sleep Controller PSC chapter 17 2 18 Emulation Considerations ...

Page 617: ...nable Register Section 17 3 1 6 2Ch C1MISCEN EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register Section 17 3 1 7 30h C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register Section 17 3 1 4 34h C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register Section 17 3 1 5 38h C2TXEN EMAC Control Module Interrupt Core 2...

Page 618: ...trol Module Interrupt Core 1 Receive Interrupts Per Millisecond Register Section 17 3 1 12 7Ch C1TXIMAX EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register Section 17 3 1 13 80h C2RXIMAX EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register Section 17 3 1 12 84h C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecon...

Page 619: ...described in Table 17 10 Figure 17 13 EMAC Control Module Software Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 10 EMAC Control Module Software Reset Register SOFTRESET Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESET Software reset bit for the EMAC Control Module Clears the interrupt status c...

Page 620: ...ion on Interrupt Core 2 0 Pacing for TX interrupts on Core 2 disabled 1 Pacing for TX interrupts on Core 2 enabled 20 C2RXPACEEN Enable pacing for RX interrupt pulse generation on Interrupt Core 2 0 Pacing for RX interrupts on Core 2 disabled 1 Pacing for RX interrupts on Core 2 enabled 19 C1TXPACEEN Enable pacing for TX interrupt pulse generation on Interrupt Core 1 0 Pacing for TX interrupts on ...

Page 621: ...r RX Channel 7 6 RXCH6THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 6 0 CnRXTHRESHPULSE generation is disabled for RX Channel 6 1 CnRXTHRESHPULSE generation is enabled for RX Channel 6 5 RXCH5THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 5 0 CnRXTHRESHPULSE generation is disabled for RX Channel 5 1 CnRXTHRESHPULSE generation is enabled for RX Channel 5 4...

Page 622: ...nabled for RX Channel 7 6 RXCH6EN Enable CnRXPULSE interrupt generation for RX Channel 6 0 CnRXPULSE generation is disabled for RX Channel 6 1 CnRXPULSE generation is enabled for RX Channel 6 5 RXCH5EN Enable CnRXPULSE interrupt generation for RX Channel 5 0 CnRXPULSE generation is disabled for RX Channel 5 1 CnRXPULSE generation is enabled for RX Channel 5 4 RXCH4EN Enable CnRXPULSE interrupt gen...

Page 623: ... enabled for TX Channel 7 6 TXCH6EN Enable CnTXPULSE interrupt generation for TX Channel 6 0 CnTXPULSE generation is disabled for TX Channel 6 1 CnTXPULSE generation is enabled for TX Channel 6 5 TXCH5EN Enable CnTXPULSE interrupt generation for TX Channel 5 0 CnTXPULSE generation is disabled for TX Channel 5 1 CnTXPULSE generation is enabled for TX Channel 5 4 TXCH4EN Enable CnTXPULSE interrupt g...

Page 624: ...ld Value Description 31 4 Reserved 0 Reserved 3 STATPENDEN Enable CnMISCPULSE interrupt generation when EMAC statistics interrupts are generated 0 CnMISCPULSE generation is disabled for EMAC STATPEND interrupts 1 CnMISCPULSE generation is enabled for EMAC STATPEND interrupts 2 HOSTPENDEN Enable CnMISCPULSE interrupt generation when EMAC host interrupts are generated 0 CnMISCPULSE generation is dis...

Page 625: ...ESHPULSE interrupt 1 RX Channel 6 satisfies conditions to generate a CnRXTHRESHPULSE interrupt 5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt 4 RXCH4THRESHSTAT Interrupt status for RX Channel 4 masked...

Page 626: ...interrupt 1 RX Channel 6 satisfies conditions to generate a CnRXPULSE interrupt 5 RXCH5STAT Interrupt status for RX Channel 5 masked by the CnRXEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXPULSE interrupt 4 RXCH4STAT Interrupt status for RX Channel 4 masked by the CnRXEN register 0 RX Channel 4 does n...

Page 627: ...E interrupt 1 TX Channel 6 satisfies conditions to generate a CnTXPULSE interrupt 5 TXCH5STAT Interrupt status for TX Channel 5 masked by the CnTXEN register 0 TX Channel 5 does not satisfy conditions to generate a CnTXPULSE interrupt 1 TX Channel 5 satisfies conditions to generate a CnTXPULSE interrupt 4 TXCH4STAT Interrupt status for TX Channel 4 masked by the CnTXEN register 0 TX Channel 4 does...

Page 628: ...eld Value Description 31 4 Reserved 0 Reserved 3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the CnMISCEN register 0 EMAC STATPEND does not satisfy conditions to generate a CnMISCPULSE interrupt 1 EMAC STATPEND satisfies conditions to generate a CnMISCPULSE interrupt 2 HOSTPENDSTAT Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register 0 EMAC HOSTPEND does not satisfy con...

Page 629: ...llisecond Register CnRXIMAX Bit Field Value Description 31 6 Reserved 0 Reserved 5 0 RXIMAX 2 3Fh RXIMAX is the desired number of CnRXPULSE interrupts generated per millisecond when CnRXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_count...

Page 630: ...Millisecond Register CnTXIMAX Bit Field Value Description 31 6 Reserved 0 Reserved 5 0 TXIMAX 2 3Fh TXIMAX is the desired number of CnTXPULSE interrupts generated per millisecond when CnTXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_cou...

Page 631: ...MDIO User Command Complete Interrupt Unmasked Register Section 17 3 2 7 24h USERINTMASKED MDIO User Command Complete Interrupt Masked Register Section 17 3 2 8 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register Section 17 3 2 9 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 17 3 2 10 80h USERACCESS0 MDIO User Access Register 0 Section 1...

Page 632: ...bles the MDIO state machine 1 Enable the MDIO state machine 29 Reserved 0 Reserved 28 24 HIGHEST_USER_CHANNEL 0 1Fh Highest user channel that is available in the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDI...

Page 633: ...n indication of the presence or not of a PHY with the corresponding address Writing a 1 to any bit will clear it writing a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY 17 3 2 4 PHY Link Status Register LINK The PHY link status register LINK is shown in Figure 17 28 ...

Page 634: ...ions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERPHY1 MDIO Link change event raw value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK registe...

Page 635: ...ed value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 and the corresponding LINKINTENB bit was set Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK register corresponding to the PHY address in MDIO user ...

Page 636: ...sked Register USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO User command complete event bit When asserted the bit indicates that the previously scheduled PHY read or write command using the USERACCESS1 register has completed Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO user command complete event 1 The previously sched...

Page 637: ...0 Reserved 1 USERACCESS1 Masked value of MDIO User command complete interrupt When asserted The bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS1 register has completed Writing a 1 will clear the interrupt writing a 0 has no effect 0 No MDIO user command complete event 1 The previously scheduled PHY read or write command using MDIO user access ...

Page 638: ...1 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user interrupt mask set for USERINTMASKED 1 Setting a bit to 1 will enable MDIO user command complete interrupts for the USERACCESS1 register MDIO user interrupt for USERACCESS1 is disabled if the corresponding bit is 0 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled 1...

Page 639: ...r Register USERINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user command complete interrupt mask clear for USERINTMASKED 1 Setting the bit to 1 will disable further user command complete interrupts for USERACCESS1 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is ...

Page 640: ...cess when it is convenient for it to do so this is not an instantaneous process Writing a 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a regis...

Page 641: ...Register 0 USERPHYSEL0 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable...

Page 642: ...cess when it is convenient for it to do so this is not an instantaneous process Writing 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a registe...

Page 643: ... Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable li...

Page 644: ...ACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 17 3 3 20 100h RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register Section 17 3 3 21 104h RXUNICASTSET Receive Unicast Enable Set Register Section 17 3 3 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 17 3 3 23 10Ch RXMAXLEN Receive Maximum Length Register Section 17 3 3 24 110h RXBUFFEROFFSET Receive B...

Page 645: ...it Channel 5 DMA Head Descriptor Pointer Register Section 17 3 3 46 618h TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 17 3 3 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 17 3 3 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 17 3 3 47 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section ...

Page 646: ...3 3 50 15 23Ch TXMCASTFRAMES Multicast Transmit Frames Register Section 17 3 3 50 16 240h TXPAUSEFRAMES Pause Transmit Frames Register Section 17 3 3 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 17 3 3 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 17 3 3 50 19 24Ch TXSINGLECOLL Transmit Single Collision Frames Register Section 17 3 3 50 20 250h TXMULTICOLL Tr...

Page 647: ...nsmit Revision ID Register TXREVID Field Descriptions Bit Field Value Description 31 0 TXREV Transmit module revision 4EC0 020Dh Current transmit revision value 17 3 3 2 Transmit Control Register TXCONTROL The transmit control register TXCONTROL is shown in Figure 17 40 and described in Table 17 39 Figure 17 40 Transmit Control Register TXCONTROL 31 16 Reserved R 0 15 1 0 Reserved TXEN R 0 R W 0 L...

Page 648: ...0 LEGEND R W Read Write R Read only n value after reset Table 17 40 Transmit Teardown Register TXTEARDOWN Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h...

Page 649: ...Receive Revision ID Register RXREVID Field Descriptions Bit Field Value Description 31 0 RXREV Receive module revision 4EC0 020Dh Current receive revision value 17 3 3 5 Receive Control Register RXCONTROL The receive control register RXCONTROL is shown in Figure 17 43 and described in Table 17 42 Figure 17 43 Receive Control Register RXCONTROL 31 16 Reserved R 0 15 1 0 Reserved RXEN R 0 R W 0 LEGE...

Page 650: ... R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 43 Receive Teardown Register RXTEARDOWN Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown register is read as 0 0 Teardown receive channel 0 1h...

Page 651: ...D TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 17 44 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND 0 1 TX6PEND raw interrupt read before mask 5 TX5PEND 0 1 TX5PEND raw interr...

Page 652: ...ed R 0 7 6 5 4 3 2 1 0 TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 17 45 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND masked interrupt read 6 TX6PEND 0 1 TX6PEND masked interrupt read 5 TX5PEND 0 ...

Page 653: ...riptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 TX4...

Page 654: ...ptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effec...

Page 655: ... only n value after reset Table 17 48 MAC Input Vector Register MACINVECTOR Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reserved 27 STATPEND 0 1 EMAC module statistics interrupt STATPEND pending status bit 26 HOSTPEND 0 1 EMAC module host error interrupt HOSTPEND pending status bit 25 LINKINT0 0 1 MDIO module USERPHYSEL0 LINKINT0 status bit 24 USERINT0 0 1 MDIO module USERACCES...

Page 656: ...MAC End Of Interrupt Vector Register MACEOIVECTOR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 INTVECT 0 1Fh Acknowledge EMAC Control Module Interrupts 0h Acknowledge C0RXTHRESH Interrupt 1h Acknowledge C0RX Interrupt 2h Acknowledge C0TX Interrupt 3h Acknowledge C0MISC Interrupt STATPEND HOSTPEND MDIO LINKINT0 MDIO USERINT0 4h Acknowledge C1RXTHRESH Interrupt 5h Ackn...

Page 657: ...ield Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND raw interrupt read before mask 14 RX6THRESHPEND 0 1 RX6THRESHPEND raw interrupt read before mask 13 RX5THRESHPEND 0 1 RX5THRESHPEND raw interrupt read before mask 12 RX4THRESHPEND 0 1 RX4THRESHPEND raw interrupt read before mask 11 RX3THRESHPEND 0 1 RX3THRESHPEND raw interrupt read before mas...

Page 658: ...set Table 17 51 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND masked interrupt read 14 RX6THRESHPEND 0 1 RX6THRESHPEND masked interrupt read 13 RX5THRESHPEND 0 1 RX5THRESHPEND masked interrupt read 12 RX4THRESHPEND 0 1 RX4THRESHPEND masked interrupt read 11 RX3THRESHPEND 0 1 RX3TH...

Page 659: ... threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask set bit Write 1 to enable interru...

Page 660: ...d mask clear bit Write 1 to disable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask clear bit Write 1 to disable inte...

Page 661: ...ion 31 2 Reserved 0 Reserved 1 HOSTPEND 0 1 Host pending interrupt HOSTPEND raw interrupt read before mask 0 STATPEND 0 1 Statistics pending interrupt STATPEND raw interrupt read before mask 17 3 3 18 MAC Interrupt Status Masked Register MACINTSTATMASKED The MAC interrupt status masked register MACINTSTATMASKED is shown in Figure 17 56 and described in Table 17 55 Figure 17 56 MAC Interrupt Status...

Page 662: ...mask set bit Write 1 to enable interrupt a write of 0 has no effect 0 STATMASK 0 1 Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 17 3 3 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 17 58 and described in Table 17 57 Figure 17 58 MAC Interrupt Mask Clear Register MACINTMASKCLE...

Page 663: ... the buffer descriptor packet length 29 RXQOSEN Receive quality of service enable bit 0 Receive QOS is disabled 1 Receive QOS is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The ...

Page 664: ...es 1h Select channel 1 to receive promiscuous frames 2h Select channel 2 to receive promiscuous frames 3h Select channel 3 to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive ...

Page 665: ...s continued Bit Field Value Description 2 0 RXMULTCH 0 7h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to...

Page 666: ...31 8 Reserved 0 Reserved 7 RXCH7EN 0 1 Receive channel 7 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 6 RXCH6EN 0 1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN 0 1 R...

Page 667: ...it Field Value Description 31 8 Reserved 0 Reserved 7 RXCH7EN 0 1 Receive channel 7 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN 0 ...

Page 668: ...frames with CRC code or alignment error are jabber frames 17 3 3 25 Receive Buffer Offset Register RXBUFFEROFFSET The receive buffer offset register RXBUFFEROFFSET is shown in Figure 17 63 and described in Table 17 62 Figure 17 63 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 62 Receive Buff...

Page 669: ...Reserved 7 0 RXFILTERTHRESH 0 FFh Receive filter low threshold These bits contain the free buffer count threshold value for filtering low priority incoming frames This field should remain 0 if no filtering is desired 17 3 3 27 Receive Channel Flow Control Threshold Registers RX0FLOWTHRESH RX7FLOWTHRESH The receive channel 0 7 flow control threshold register RXnFLOWTHRESH is shown in Figure 17 65 a...

Page 670: ...ield Value Description 31 16 Reserved 0 Reserved 15 0 RXnFREEBUF 0 FFh Receive free buffer count These bits contain the count of free buffers available The RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enable...

Page 671: ...th word 1 Block all EMAC DMA controller writes to the receive buffer descriptor offset buffer length words during packet processing When this bit is set the EMAC will never write the third word to any receive buffer descriptor 13 RXOWNERSHIP Receive ownership write bit value 0 The EMAC writes the Receive ownership bit to 0 at the end of packet processing 1 The EMAC writes the Receive ownership bit...

Page 672: ...rdless of this bit setting The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory 0 Transmit flow control is disabled Full duplex mode incoming pause frames are not acted upon 1 Transmit flow control is enabled Full duplex mode incoming pause frames are acted upon 3 RXBUFFERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled Half ...

Page 673: ... DMA related host errors The host should read this field after a host error interrupt HOSTPEND to determine the error Host error interrupts require hardware reset in order to recover A 0 packet length is an error but it is not detected 0 No error 1h SOP error the buffer is the first buffer in a packet but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer...

Page 674: ...ed on receive channel 3 4h The host error occurred on receive channel 4 5h The host error occurred on receive channel 5 6h The host error occurred on receive channel 6 7h The host error occurred on receive channel 7 7 3 Reserved 0 Reserved 2 RXQOSACT Receive Quality of Service QOS active bit When asserted indicates that receive quality of service is enabled and that at least one channel freebuffer...

Page 675: ...d in conjunction with SOFT bit to determine the emulation suspend mode 0 Free running mode is disabled During emulation halt SOFT bit determines operation of EMAC 1 Free running mode is enabled During emulation halt EMAC continues to operate 17 3 3 32 FIFO Control Register FIFOCONTROL The FIFO control register FIFOCONTROL is shown in Figure 17 70 and described in Table 17 69 Figure 17 70 FIFO Cont...

Page 676: ... of cells in the receive FIFO 15 8 ADDRESSTYPE 2h Address type 7 0 MACCFIG 2h MAC configuration value 17 3 3 34 Soft Reset Register SOFTRESET The soft reset register SOFTRESET is shown in Figure 17 72 and described in Table 17 71 Figure 17 72 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 71 Soft R...

Page 677: ...5 8 MACSRCADDR0 0 FFh MAC source address lower 8 0 bits byte 0 7 0 MACSRCADDR1 0 FFh MAC source address bits 15 8 byte 1 17 3 3 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source address high bytes register MACSRCADDRHI is shown in Figure 17 74 and described in Table 17 73 Figure 17 74 MAC Source Address High Bytes Register MACSRCADDRHI 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R W 0 ...

Page 678: ...t into a 64 bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 17 75 and described in Table 17 74 Figure 17 75 MAC Hash Address Register 1 MACHASH1 31 0 MACHASH1 R W 0 LEGEND R W Read Write n value after reset Table 17 74 MAC Hash Address Register 1 MACHASH1 Field Descripti...

Page 679: ...unter to be observed for test purposes This field is loaded automatically according to the backoff algorithm and is decremented by one for each slot time after the collision 17 3 3 40 Transmit Pacing Algorithm Test Register TPACETEST The transmit pacing algorithm test register TPACETEST is shown in Figure 17 78 and described in Table 17 77 Figure 17 78 Transmit Pacing Algorithm Test Register TPACE...

Page 680: ...sends an outgoing pause frame with pause time of FFFFh The receive pause timer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and the load decrement process is repeated 17 3 3 42 Transmit Pause Timer Register TXPAUSE The transmit pause timer register TXPAUSE is shown in Figure 17 80 and described in Table 17 79 Figure 17 8...

Page 681: ...ytes Register MACADDRLO Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 VALID Address valid bit This bit should be cleared to zero for unused address channels 0 Address is not valid and will not be used for matching or filtering incoming packets 1 Address is valid and will be used for matching or filtering incoming packets 19 MATCHFILT Match or filter bit 0 The address ...

Page 682: ...40 byte 5 Bit 40 is the group bit It is forced to 0 and read as 0 Therefore only unicast addresses are represented in the address table 17 3 3 45 MAC Index Register MACINDEX The MAC index register MACINDEX is shown in Figure 17 83 and described in Table 17 82 Figure 17 83 MAC Index Register MACINDEX 31 16 Reserved R 0 15 3 2 0 Reserved MACINDEX R 0 R W 0 LEGEND R W Read Write R Read only n value a...

Page 683: ...perations in the queue for the selected channel Writing to these locations when they are nonzero is an error except at reset Host software must initialize these locations to 0 on reset 17 3 3 47 Receive Channel DMA Head Descriptor Pointer Registers RX0HDP RX7HDP The receive channel 0 7 DMA head descriptor pointer register RXnHDP is shown in Figure 17 85 and described in Table 17 84 Figure 17 85 Re...

Page 684: ...ith the buffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be deasserted 17 3 3 49 Receive Channel Completion Pointer Registers RX0CP RX7CP The receive channel 0 7 completion pointer register RXnCP is shown in Figure 17 87 and described in Table 17 86 Figure 17 87 Receive Channel n Com...

Page 685: ...GEND R W Read Write WD Write to decrement n value after reset 17 3 3 50 1 Good Receive Frames Register RXGOODFRAMES The total number of good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CRC e...

Page 686: ...d due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no alignment or code error Had a CRC error A CRC error is defined as having all of the following A frame containing an even number of nibbles Fails the frame check sequence test See Section 17 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 17 3 3 50 6 Receive Alignment Code ...

Page 687: ...ived on the EMAC An undersized frame is defined as having all of the following Was any data frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was less than 64 bytes long Had no CRC error alignment error or code error See Section 17 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 17 3 3 50 10 Receive Frame...

Page 688: ...frame destination channel flow control threshold register RXnFLOWTHRESH value was greater than or equal to the channel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN bit is set in RXMBPENABLE Had no CRC error alignment error or code error See Section 17 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 17...

Page 689: ... frames are only transmitted in full duplex mode carrier loss and collisions have no effect on this statistic Transmitted pause frames are always 64 byte multicast frames so appear in the multicast transmit frames register and 64 octect frames register statistics 17 3 3 50 18 Deferred Transmit Frames Register TXDEFERRED The total number of frames transmitted on the EMAC that first experienced defe...

Page 690: ...r of frames when transmission was abandoned due to excessive collisions Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced 16 collisions before abandoning all attempts at transmitting the frame None of the collisions were late CRC errors have no...

Page 691: ...ss Did not experience late collisions excessive collisions underrun or carrier sense error Was exactly 64 bytes long If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted then the frame is recorded in this statistic CRC errors alignment code errors and overruns do not affect the recording of frames in this statistic 17 3 3 50 28 Tra...

Page 692: ...4 to RXMAXLEN Octet Frames Register FRAME1024TUP The total number of 1024 byte to RXMAXLEN byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 1024 bytes to RXMA...

Page 693: ...verrun frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of any size including less than 64 byte and greater than RXMAXLEN byte frames The EMAC was unable to receive it because it did not have the resources to receive it cell FIFO full or no DMA buffer available after the fr...

Page 694: ... March 2013 Revised September 2016 External Memory Interface A EMIFA This chapter describes the external memory interface A EMIFA The EMIFA SDRAM interface is not supported on all devices see your device specific data manual to see if the EMIFA SDRAM is supported on your device Topic Page 18 1 Introduction 695 18 2 Architecture 695 18 3 Example Configuration 736 18 4 Registers 758 ...

Page 695: ...8 3 contains an example of operating the EMIFA in this configuration 18 1 2 Features The EMIFA includes many features to enhance the ease and flexibility of connecting to external SDR SDRAM and asynchronous devices For details on features of EMIFA see your device specific data manual 18 1 3 Functional Block Diagram Figure 18 1 illustrates the connections between the EMIFA and its internal requeste...

Page 696: ...ription EMA_D x 0 I O EMIFA data bus The number of available data bus pins varies among devices see your device specific data manual for details EMA_ A x 0 O EMIFA address bus The number of available address pins varies among devices see your device specific data manual for details When interfacing to an SDRAM device these pins are primarily used to provide the row and column address to the SDRAM ...

Page 697: ...2 1 for details on the clock signal Table 18 3 EMIFA Pins Specific to Asynchronous Memory Pin s I O Description EMA_CS 5 2 O Active low chip enable pins for asynchronous devices These pins are meant to be connected to the chip select pins of the attached asynchronous device These pins are active only during accesses to the asynchronous memory EMA_WAIT I Wait input with programmable polarity NAND F...

Page 698: ...r bank for the current access READ Read The READ command outputs the starting column address and signals the SDRAM to begin the burst read operation Address EMA_A 10 is always pulled low to avoid auto precharge This allows for better bank interleaving performance WRT Write The WRT command outputs the starting column address and signals the SDRAM to begin the burst write operation Address EMA_A 10 ...

Page 699: ...or 11 See your device specific data manual for the number of column address bits supported on your device The number of row address bits is 13 14 15 or 16 See your device specific data manual for the number of row address bits supported on your device The number of internal banks is 1 2 or 4 See your device specific data manual for the number of internal banks supported on your device Figure 18 3 ...

Page 700: ...re www ti com 700 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 3 EMIFA to 2M 16 4 bank SDRAM Interface Figure 18 4 EMIFA to 512K 16 2 bank SDRAM Interface Table 18 6 16 bit EMIFA Address Pin Connections SDRAM Size Width Banks Device Address Pins 16M bits 16 2 SDRAM A 10 0 EMIF...

Page 701: ...th PD when entering power down mode NM Narrow Mode This bit defines the width of the data bus between the EMIFA and the attached SDRAM device When set to 1 the data bus is set to 16 bits When set to 0 the data bus is set to 32 bits This bit must always be set to 1 CL CAS latency This field defines the number of clock cycles between when an SDRAM issues a READ command and when the first piece of da...

Page 702: ...s to the SDRAM and Asynchronous interfaces are performed until this auto initialization is complete A write is performed to any of the three least significant bytes of the SDRAM configuration register SDCR An SDRAM initialization sequence consists of the following steps 1 If the initialization sequence is activated by a write to SDCR and if any of the SDRAM banks are open the EMIFA issues a PRE co...

Page 703: ... NOT violated 1 Place the SDRAM into Self Refresh Mode by setting the SR bit of SDCR to 1 A byte write to the upper byte of SDCR should be used to avoid restarting the SDRAM Auto Initialization Sequence described in Section 18 2 4 4 The SDRAM should be placed into Self Refresh mode when changing the frequency of EMA_CLK to avoid incurring the 200 μs Power up constraint again 2 Program the CPU s PL...

Page 704: ...inder of this section details the EMIFA s refresh scheme and provides an example for determining the appropriate value to place in the RR field of SDRCR The two counters used to perform auto refresh cycles are a 13 bit refresh interval counter and a 4 bit refresh backlog counter At reset and upon writing to the RR field the refresh interval counter is loaded with the value from RR field and begins...

Page 705: ...by setting the SR bit of SDCR to 1 This will cause the EMIFA to issue the SLFR command after completing any outstanding SDRAM access requests and clearing the refresh backlog counter by performing one or more auto refresh cycles This places the attached SDRAM device into self refresh mode in which it consumes a minimal amount of power while performing its own refresh cycles The SR bit should be se...

Page 706: ...anks of the SDRAM are closed precharged prior to issuing the POWER DOWN command Therefore the EMIFA only supports Precharge Power Down The EMIFA does not support Active Power Down where internal banks of the SDRAM are open active before the POWER DOWN command is issued During the power down state the EMIFA services the SDRAM asynchronous memory and register accesses as normal returning to the powe...

Page 707: ...s configured to 16 bit by setting the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 18 5 shows a burst size of eight The EMIFA will truncate a series of bursting data if the remaining addresses of the burst are not required to complete the request The EMIFA can truncate the burst in three ways By issuing another READ to the same page in the same bank By ...

Page 708: ...g the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 18 6 shows a burst size of eight Figure 18 6 Timing Waveform for Basic SDRAM Write Operation The EMIFA will truncate a series of bursting data if the remaining addresses of the burst are not part of the write request The EMIFA can truncate the burst in three ways By issuing another WRT to the same page ...

Page 709: ...close it This method of traversal through the SDRAM banks helps maximize the number of open banks inside of the SDRAM and results in an efficient use of the device There is no limitation on the number of banks that can be open at one time but only one page within a bank can be open at a time The EMIFA uses the EMA_WE_DQM pins during a WRT command to mask out selected bytes or entire words The EMA_...

Page 710: ... only during the strobe period of an access In this mode the EMA_WE_DQM pins of the EMIFA function as standard byte enables for reads and writes A summary of the differences between the two modes of operation are shown in Table 18 14 Refer to Section 18 2 5 4 for the details of asynchronous operations in Normal Mode and to Section 18 2 5 5 for the details of asynchronous operations in Select Strob...

Page 711: ... the least significant bits of the halfword or byte address respectively Additionally when the EMIFA interfaces to a 16 bit asynchronous device the EMA_BA 0 pin can serve as the upper address line EMA_A 22 Note that the width of the address bus varies with devices therefore see your device specific data manual for the EMA_A bus width supported Figure 18 8 and Figure 18 9 show the mapping between t...

Page 712: ...the EMIFA s asynchronous interface can be configured by programming the appropriate register fields The reset value and bit position for each register field can be found in Section 18 4 but the Boot ROM documentation should be consulted to determine if the fields are programmed during boot The following tables list the register fields that can be programmed and describe the purpose of each field T...

Page 713: ...ld time for the data pins EMA_D Refer to the datasheet of the external asynchronous device to determine the appropriate setting for this field TA Minimum turnaround time This field defines the minimum number of EMIFA clock cycles between asynchronous reads and writes minus one cycle The purpose of this feature is to avoid contention on the bus The value written to this field also determines the nu...

Page 714: ...d of an access cycle The maximum number of EMIFA clock cycles it will wait is determined by the following formula Maximum Extended Wait Cycles MAX_EXT_WAIT 1 16 If the EMA_WAIT pin is not deactivated within the time specified by this field the EMIFA resumes the access cycle registering whatever data is on the bus and proceeding to the hold period of the access cycle This situation is referred to a...

Page 715: ...ous Read Operations Normal Mode NOTE During the entirety of an asynchronous read operation the EMA_WE pin is driven high An asynchronous read is performed when any of the requesters mentioned in Section 18 2 2 request a read from the attached asynchronous memory After the request is received a read operation is initiated once it becomes the EMIFA s highest priority task according to the priority s...

Page 716: ...eriod EMA_OE rises The data on the EMA_D bus is sampled by the EMIFA In Figure 18 10 EMA_WAIT is inactive If EMA_WAIT is instead activated the strobe period can be extended by the external device to give it more time to provide the data Section 18 2 5 7 contains more details on using the EMA_WAIT pin End of the hold period At the end of the hold period The address pins EMA_A and EMA_BA become inva...

Page 717: ...MIFA proceeds to the setup period of the operation If it is no longer the highest priority task the EMIFA terminates the operation Start of the setup period The following actions occur at the start of the setup period The setup strobe and hold values are set according to the W_SETUP W_STROBE and W_HOLD values in CEnCFG The address pins EMA_A and EMA_BA and the data pins EMA_D become valid The EMA_...

Page 718: ...ress Data Address Byte enable Architecture www ti com 718 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 11 Timing Waveform of an Asynchronous Write Cycle in Normal Mode ...

Page 719: ...ptions to this rule If the current read operation was directly proceeded by another read operation to the same chip select no turn around cycles are inserted After the EMIFA has waited for the turn around cycles to complete it again checks to make sure that the read operation is still its highest priority task If so the EMIFA proceeds to the setup period of the operation If it is no longer the hig...

Page 720: ...e enables Address Data Architecture www ti com 720 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 12 Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...

Page 721: ...o make sure that the write operation is still its highest priority task If so the EMIFA proceeds to the setup period of the operation If it is no longer the highest priority task the EMIFA terminates the operation Start of the setup period The following actions occur at the start of the setup period The setup strobe and hold values are set according to the W_SETUP W_STROBE and W_HOLD values in CEn...

Page 722: ...e enables Address Data Architecture www ti com 722 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 13 Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...

Page 723: ...art an ECC calculation for EMA_CS 4 Cleared to 0 when NAND Flash 3 ECC register NANDF3ECC is read CS4NAND NAND Flash mode for EMA_CS 4 Set to 1 to enable NAND Flash mode for EMA_CS 4 CS3ECC NAND Flash ECC state for EMA_CS 3 Set to 1 to start an ECC calculation for EMA_CS 3 Cleared to 0 when NAND Flash 2ECC register NANDF2ECC is read CS3NAND NAND Flash mode for EMA_CS 3 Set to 1 to enable NAND Flas...

Page 724: ...ed to EMIFA base address 0000 0000h to drive CLE and ALE low 0000 0010h to drive CLE high and ALE low 0000 0008h to drive CLE low and ALE high 18 2 5 6 4 NAND Read and Program Operations A NAND Flash access cycle is composed of a command address and data phase The EMIFA will not automatically generate these three phases to complete a NAND access with one transfer request To complete a NAND access ...

Page 725: ...LE and or ALE high To prevent the address from incrementing into a range that drives CLE and or ALE high the EDMA ACNT BCNT SIDX DIDX and synchronization type must be programmed appropriately Following is an example configuration of EDMA controller when EMA_A 2 is connected to CLE and EMA_A 1 is connected to ALE EDMA setup for a NAND Flash data read ACNT 8 bytes this can also be set to less than o...

Page 726: ... ECC start bit 4BITECC_START is cleared upon reading any of the NAND Flash 4 bit ECC 1 4 registers NAND4BITECC 4 1 The NAND Flash 4 bit ECC 1 4 registers are cleared upon writing one to the 4 bit ECC start bit 4BITECC_START The 4 bit ECC algorithm works on a 10 bit data bus but only the lower eight bits of the data bus actually contain data When the EMIFA is used in 16 bit mode the lower and upper...

Page 727: ... value can be broken down into ten 8 bit values 5 Store the parity to spare location in the NAND Flash For reads 1 Set the 4BITECC_START bit in the NAND Flash control register NANDFCR to 1 2 Read 518 bytes of data from the NAND Flash 3 Clear the 4BITECC_START bit in NANDFCR by reading any of the NAND Flash 4 bit ECC registers 4 Read the parity stored in the spare location in the NAND Flash 5 Conve...

Page 728: ...peration has completed the software can then configure the selected GPIO to be high 18 2 5 7 Extended Wait Mode and the EMA_WAIT Pin The EMIFA supports the Extend Wait Mode This is a mode in which the external asynchronous device may assert control over the length of the strobe period The Extended Wait Mode can be entered by setting the EW bit in the asynchronous n configuration register CEnCFG n ...

Page 729: ...al pull ups such as 10kΩ resistors should be placed on the 16 EMIFA data bus pins which do not have internal pull ups if it is required to perform reads in this situation The precise resistor value should be chosen so that the worst case combined off state leakage currents do not cause the voltage levels on the associated pins to drop below the high level input voltage requirement For information ...

Page 730: ...ation register AWCC The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert the EMA_WAIT pin within the number of cycles defined by the MAX_EXT_WAIT bit in AWCC this happens only in extended wait mode EMIFA supports only linear incrementing and cache line wrap addressing modes If an access request for an unsupported addressing mode is received t...

Page 731: ... been enabled by writing a 1 to the LT_MASK_SET bit in INTMSKSET EMIFA interrupt mask set register INTMSKSET WR_MASK_SET Writing a 1 to this bit enables the wait rise interrupt AT_MASK_SET Writing a 1 to this bit enables the asynchronous timeout interrupt LT_MASK_SET Writing a 1 to this bit enables the line trap interrupt EMIFA interrupt mask clear register INTMSKCLR WR_MASK_CLR Writing a 1 to thi...

Page 732: ...s according to the following priority scheme highest priority listed first 1 If the EMIFA s backlog refresh counter is at the Refresh Must urgency level the EMIFA performs multiple SDRAM auto refresh cycles until the Refresh Release urgency level is reached 2 If an SDRAM or asynchronous read has been requested the EMIFA performs a read operation 3 If the EMIFA s backlog refresh counter is at the R...

Page 733: ... the asynchronous request is determined by the programmed setup strobe hold and turnaround values but can also be extended with the assertion of the EMA_WAIT input signal up to a programmed maximum limit It is up to the user to make sure that an entire asynchronous request does not exceed the timing values listed above when also interfacing to an SDRAM device This can be done by limiting the async...

Page 734: ...sh mode If the external memory requires a continuous clock the clock provided by the PLL must not be turned off because this may result in data corruption See the following subsections for the proper procedures to follow when stopping the EMIFA memory controller clocks Figure 18 17 EMIFA PSC Block Diagram 18 2 14 1 Power Management Using Self Refresh Mode The EMIFA can be placed into a self refres...

Page 735: ...e request and returns back to auto sleep state until further requests come On frequent requests EMIFA switches between auto sleep and enable states To bring EMIFA back to the enable state auto wake can be used Following procedure is followed for performing auto wake Program the LPSC of EMIFA for auto wake Bring EMIFA out of self refresh Refer to Section 18 2 4 7 for details on self refresh mode Af...

Page 736: ...de use of to receive the RD BY signal coming from the second flash as shown in Figure 18 18 Finally this example configuration connects the EMA_WE pin to the WE input of the flash and operates the EMIFA in Normal Mode 18 3 2 Software Configuration The following sections describe how to interface the EMIFA to SDRAM Asynchronous SRAM ASRAM or a NAND Flash device 18 3 2 1 Configuring the SDRAM Interf...

Page 737: ...4 bank CE CAS RAS WE CLK CKE BA 1 BA 0 A 11 0 LDQM UDQM DQ 15 0 TC5515100FT 12 A 0 A 19 1 DQ 15 0 CE WE OE RY BY BYTE0 BYTE1 www ti com Example Configuration 737 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 18 Example Configuration Interface ...

Page 738: ...tead Samsung specifies tRC as the minimum auto refresh period 2 The Samsung datasheet does not specify a tWR value Instead Samsung specifies tRDL as last data in to row precharge minimum delay Table 18 27 SDTIMR Field Calculations for the EMIFA to K4S641632H TC L 70 Interface Field Name Formula Value from K4S641632H TC L 70 Datasheet Value Calculated for Field T_RFC T_RFC tRFC fEMA_CLK 1 tRC 68 ns...

Page 739: ...rmula Value from K4S641632H TC L 70 Datasheet Value Calculated for Field T_XS T_XS tXSR fEMA_CLK 1 tRC 68 ns min 1 6 Figure 18 20 SDRAM Self Refresh Exit Timing Register SDSRETR 31 16 0000 0000 0000 0000 Reserved 15 5 4 0 000 0000 0000 0 0110 Reserved T_XS 18 3 2 1 4 SDRAM Refresh Control Register SDRCR Settings for the EMIFA to K4S641632H TC L 70 Interface The SDRAM refresh control register SDRCR...

Page 740: ...ld be programmed The EMIFA is now ready to perform read and write accesses to the SDRAM Table 18 30 SDCR Field Values For the EMIFA to K4S641632H TC L 70 Interface Field Value Purpose SR 0 To avoid placing the EMIFA into the self refresh state NM 1 To configure the EMIFA for a 16 bit data bus CL 011b To select a CAS latency of 3 BIT11_9LOCK 1 To allow the CL field to be written IBANK 010b To selec...

Page 741: ...MIFA Input Timing Requirements Parameter Description tSU Data Setup time data valid before EMA_OE high tH Data Hold time data valid after EMA_OE high Table 18 32 ASRAM Output Timing Characteristics Parameter Description tACC Address Access time tOH Output data Hold time for address change tCOD Output Disable time from chip enable Table 18 33 ASRAM Input Timing Requirement for a Read Parameter Desc...

Page 742: ...nst the situation when the output turn off time of the memory is longer than the time it takes to start the next write cycle If this is the case the EMIFA will drive data at the same time as the memory causing contention on the bus By examining Figure 18 23 the equation for TA can be derived as Figure 18 23 Timing Waveform of an ASRAM Read For a write access Table 18 34 lists the AC timing specifi...

Page 743: ...how the EMIFA and ASRAM AC timing requirements work together to define values for W_SETUP W_STROBE and W_HOLD From Figure 18 24 the following equations may be derived tcyc is the period at which the EMIFA operates The W_SETUP W_STROBE and W_HOLD fields are programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of...

Page 744: ...epresents the delayed signal seen at the ASRAM Table 18 35 ASRAM Timing Requirements With PCB Delays Parameter Description Read Access tEM_CS Delay on EMA_CS from EMIFA to ASRAM EMA_CS is driven by EMIF tEM_A Delay on EMA_A from EMIFA to ASRAM EMA_A is driven by EMIF tEM_OE Delay on EMA_OE from EMIFA to ASRAM EMA_OE is driven by EMIF tEM_D Delay on EMA_D from ASRAM to EMIFA EMA_D is driven by ASRA...

Page 745: ... EMIFA Figure 18 25 Timing Waveform of an ASRAM Read with PCB Delays From Figure 18 26 the following equations may be derived tcyc is the period at which the EMIFA operates The W_SETUP W_STROBE and W_HOLD fields are programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of tcyc in the denominator of the following...

Page 746: ...STROBE W_HOLD w tWC m tcyc 3 W_HOLD w maxǒǒtEM_WE tWR m tEM_A Ǔ tcyc ǒtEM_WE tDH m tEM_D Ǔ tcyc Ǔ 1 W_SETUP W_STROBE max tEM_A tAW m tEM_WE tcyc tEM_D tDS m tEM_WE tcyc 2 W_STROBE w tWP m tcyc 1 Example Configuration www ti com 746 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 ...

Page 747: ...er Description Min Max Units tACC Address Access time 12 nS tOH Output data Hold time for address change 3 nS tRC Read cycle time 12 nS tWP Write Pulse width 8 nS tAW Address valid to end of Write 9 nS tDS Data Setup time 7 nS tWR Write Recovery time 0 nS tDH Data Hold time 0 nS tWC Write Cycle time 12 nS tCOD Output Disable time from chip enable 7 Table 18 38 lists the values of the PCB board del...

Page 748: ... m tEM_A Ǔ tcyc 1 w 0 0 45 3 0 27 10 1 w 1 37 R_SETUP R_STROBE R_HOLD w tRC m tcyc 3 w ǒ12 10 Ǔ 3 w 1 8 R_SETUP R_STROBE tEM_A tACC m tSU tEM_D tcyc 2 0 27 12 5 0 45 10 2 0 23 Example Configuration www ti com 748 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Inserting these values into t...

Page 749: ...TROBE 0 W_HOLD R_HOLD Read Write hold widths W_HOLD 0 R_HOLD 0 TA Minimum turnaround time TA 0 ASIZE Asynchronous Device Bus Width ASIZE 1 select a 16 bit data bus width 18 3 2 3 Interfacing to NAND Flash The following example explains how to interface the EMIFA to the Hynix HY27UA081G1M NAND Flash device 18 3 2 3 1 Margin Requirements The Flash interface is typically a low performance interface c...

Page 750: ...by the EMIFA The command and address phases of a NAND Flash access cycle are asynchronous writes performed by the EMIFA where as the data phase can be either an asynchronous write or a read depending on whether the NAND Flash is being programmed or read Therefore to determine the required EMIFA configuration to interface to the NAND Flash for a read operation Table 18 41 and Table 18 42 list the A...

Page 751: ...re programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of tcyc in the denominator of the following equations A minus 1 is included in the equations because each field in CEnCFG is programmed in terms of EMIFA clock cycles minus 1 cycle For example R_SETUP is equal to R_SETUP width in EMIFA clock cycles minus 1...

Page 752: ...meter Description tWP Write Pulse width tCLS CLE Setup time tALS ALE Setup time tCS CS Setup time tDS Data Setup time tCLH CLE Hold time tALH ALE Hold time tCH CS Hold time tDH Data Hold time tWC Write Cycle time Figure 18 28 to Figure 18 30 show the command latch address latch and data input latch of the NAND access From Figure 18 28 to Figure 18 30 the following equations may be derived tcyc is ...

Page 753: ..._EM_A 2 EMA_WE EMA_D 7 0 tCS m tALS m tCLS m tDS m tDH m Setup Strobe Hold www ti com Example Configuration 753 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 28 Timing Waveform of a NAND Flash Command Write Figure 18 29 Timing Waveform of a NAND Flash Address Write ...

Page 754: ...S m tCLS m tDS m tDH m Setup Strobe Hold Example Configuration www ti com 754 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 18 30 Timing Waveform of a NAND Flash Data Write ...

Page 755: ...ice specific data manual for the value Table 18 44 EMIFA Timing Requirements for HY27UA081G1M Example Parameter Description Min Max Units tSU Data Setup time data valid before EMA_OE high 3 to 7 1 nS tH Data Hold time data valid after EMA_OE high 0 nS Table 18 45 NAND Flash Timing Requirements for HY27UA081G1M Example Parameter Description Min Max Units tRP Read Pulse width 60 nS tREA Read Enable ...

Page 756: ...yc 2 75 5 10 2 6 R_STROBE w maxǒǒtREA m tSU Ǔ tcyc tRP tcyc Ǔ 1 w ǒ65 10 Ǔ 1 w 5 5 R_SETUP w tCLR m tcyc 1 w ǒ10 10 Ǔ 1 w 0 Example Configuration www ti com 756 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Inserting these values into the equations defined above allows you to determine t...

Page 757: ...ous device bus width ASIZE 0 select an 8 bit data bus width Since this is a NAND Flash example the EMIFA must be configured for NAND Flash mode This is accomplished by configuring the NAND Flash control register NANDFCR as in Table 18 47 In NANDFCR chip select space 2 must be configured with NAND Flash mode enabled Table 18 47 Configuring NANDFCR for HY27UA081G1M Example Parameter Setting CS5ECC N...

Page 758: ...8 4 5 18h CE4CFG Asynchronous 3 Configuration Register Section 18 4 5 1Ch CE5CFG Asynchronous 4 Configuration Register Section 18 4 5 20h SDTIMR SDRAM Timing Register Section 18 4 6 3Ch SDSRETR SDRAM Self Refresh Exit Timing Register Section 18 4 7 40h INTRAW EMIFA Interrupt Raw Register Section 18 4 8 44h INTMSK EMIFA Interrupt Mask Register Section 18 4 9 48h INTMSKSET EMIFA Interrupt Mask Set R...

Page 759: ...it cycle configuration register AWCC is used to configure the parameters for extended wait cycles Both the polarity of the EMA_WAIT pin s and the maximum allowable number of extended wait cycles can be configured The AWCC is shown in Figure 18 32 and described in Table 18 50 Not all devices support both EMA_WAIT 1 and EMA_WAIT 0 see the device specific data manual to determine support on each devi...

Page 760: ...ternal wait states 2h 3h Reserved 21 20 CS4_WAIT 0 3h Chip Select 4 WAIT signal selection This signal determines which EMA_WAIT n signal will be used for memory accesses to chip select 4 memory space 0 EMA_WAIT 0 pin is used to control external wait states 1h EMA_WAIT 1 pin is used to control external wait states 2h 3h Reserved 19 18 CS3_WAIT 0 3h Chip Select 3 WAIT signal selection This signal de...

Page 761: ...d in Section 18 2 4 7 The field should be written using a byte write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence 0 Writing a 0 to this bit will cause connected SDRAM devices and the EMIFA to exit the Self Refresh mode 1 Writing a 1 to this bit will cause connected SDRAM devices and the EMIFA to enter the Self Refresh mode 30 PD Power Down bit This bit controls e...

Page 762: ...s read as 0 Writing to this field triggers the SDRAM initialization sequence 0 CL cannot be written 1 CL can be written 7 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 6 4 IBANK 0 7h Internal SDRAM Bank size This field defines number of banks inside the connected SDRAM devices Writing to this field triggers the SDRAM ...

Page 763: ...in Figure 18 34 and described in Table 18 52 Figure 18 34 SDRAM Refresh Control Register SDRCR 31 16 Reserved R 0 15 13 12 0 Reserved RR R 0 R W 4E2h LEGEND R W Read Write R Read only n value after reset Table 18 52 SDRAM Refresh Control Register SDRCR Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field alw...

Page 764: ... Configuration Register CEnCFG Field Descriptions Bit Field Value Description 31 SS Select Strobe bit This bit defines whether the asynchronous interface operates in Normal Mode or Select Strobe Mode See Section 18 2 5 for details on the two modes of operation 0 Normal Mode enabled 1 Select Strobe Mode enabled 30 EW Extend Wait bit This bit defines whether extended wait cycles will be enabled See ...

Page 765: ...ion 18 2 5 3 for details 0h Divide by 1 1h Divide by 2 2h 3Fh Divide by 3 to Divide by 64 6 4 R_HOLD 0 7h Read hold width in the format n 1 where n number of EMA_CLK cycles See Section 18 2 5 3 for details 0h Divide by 1 1h Divide by 2 2h 7h Divide by 3 to Divide by 8 3 2 TA 0 3h Minimum Turn Around time This field defines the minimum number of EMA_CLK cycles between reads and writes minus one cyc...

Page 766: ...ved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 22 20 T_RCD 0 7h Specifies the Trcd value of the SDRAM This defines the minimum number of EMA_CLK cycles from Active ACTV to Read READ or Write WRT minus 1 T_RCD Trcd tEMA_CLK 1 19 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always...

Page 767: ...the EMIFA issues another command The SDSRETR is shown in Figure 18 37 and described in Table 18 55 Figure 18 37 SDRAM Self Refresh Exit Timing Register SDSRETR 31 16 Reserved R 0 15 5 4 0 Reserved T_XS R 0 R W 9h LEGEND R W Read Write R Read only n value after reset Table 18 55 SDRAM Self Refresh Exit Timing Register SDSRETR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved T...

Page 768: ...3 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 WR Wait Rise This bit is set to 1 by hardware to indicate that a rising edge on the EMA_WAIT pin has occurred 0 Indicates that a rising edge has not occurred on the EMA_WAIT pin Writing a 0 has no effect 1 Indicates that a rising edge has occurred on the EMA_WAIT pin W...

Page 769: ...ways read as 0 If writing to this field always write the default value of 0 2 WR_MASKED Wait Rise Masked This bit is set to 1 by hardware to indicate a rising edge has occurred on the EMA_WAIT pin provided that the WR_MASK_SET bit is set to 1 in the EMIFA interrupt mask set register INTMSKSET 0 Indicates that a wait rise interrupt has not been generated Writing a 0 has no effect 1 Indicates that a...

Page 770: ...ASK_SET Wait Rise Mask Set This bit determines whether or not the wait rise Interrupt is enabled Writing a 1 to this bit sets this bit sets the WR_MASK_CLR bit in the EMIFA interrupt mask clear register INTMSKCLR and enables the wait rise interrupt To clear this bit a 1 must be written to the WR_MASK_CLR bit in INTMSKCLR 0 Indicates that the wait rise interrupt is disabled Writing a 0 has no effec...

Page 771: ...t clears this bit clears the WR_MASK_SET bit in the EMIFA interrupt mask set register INTMSKSET and disables the wait rise interrupt To set this bit a 1 must be written to the WR_MASK_SET bit in INTMSKSET 0 Indicates that the wait rise interrupt is disabled Writing a 0 has no effect 1 Indicates that the wait rise interrupt is enabled Writing a 1 clears this bit and the WR_MASK_SET bit in the EMIFA...

Page 772: ...START Nand Flash 4 bit ECC start for the selected chip select Set to 1 to start 4_bit ECC calculation on data for NAND Flash on chip select selected by bit 4BITECCSEL This bit is cleared when ay of the NAND Flash 4_bit ECC registers are read 1 start 4_bit ECC calculation on data for NAND Flash on chip select selected by bit 4BITECCSEL 11 CS5ECC NAND Flash ECC start for chip select 5 Set to 1 to st...

Page 773: ...t on which 4 bit ECC will be calculated 0 ECC will be calculated for CS2 1h ECC will be calculated for CS3 2h ECC will be calculated for CS4 3h ECC will be calculated for CS5 3 CS5NAND NAND Flash mode for chip select 5 0 Not using NAND Flash 1 Using NAND Flash on EMA_CS5 2 CS4NAND NAND Flash mode for chip select 4 0 Not using NAND Flash 1 Using NAND Flash on EMA_CS4 1 CS3NAND NAND Flash mode for c...

Page 774: ...4 Bit ECC Error Address and Error Value Calculation 0 1 error found 1h 2 errors found 2h 3 errors found 3h 4 errors found 15 12 Reserved 0 Reserved 11 8 ECC_STATE 0 Fh ECC correction state while performing 4 bit ECC Address and Error Value Calculation 0 No errors detected 1h Errors cannot be corrected 5 or more 2h Error correction complete errors on bit 8 or 9 3h Error correction complete error ex...

Page 775: ...ulated while reading writing NAND Flash 24 P256O 0 1 ECC code calculated while reading writing NAND Flash 23 P128O 0 1 ECC code calculated while reading writing NAND Flash 22 P64O 0 1 ECC code calculated while reading writing NAND Flash 21 P32O 0 1 ECC code calculated while reading writing NAND Flash 20 P16O 0 1 ECC code calculated while reading writing NAND Flash 19 P8O 0 1 ECC code calculated wh...

Page 776: ...s shown in Figure 18 45 and described in Table 18 63 Figure 18 45 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD 31 16 Reserved R 0 15 10 9 0 Reserved 4BITECCLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 63 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 4BITECCLOAD 0 3FFh 4 bit ECC ...

Page 777: ...ue Description 31 26 Reserved 0 Reserved 25 16 4BITECCVAL2 0 3FFh Calculated 4 bit ECC or Syndrom Value2 15 10 Reserved 0 Reserved 9 0 4BITECCVAL1 0 3FFh Calculated 4 bit ECC or Syndrom Value1 18 4 17 NAND Flash 4 Bit ECC Register 2 NAND4BITECC2 The NAND Flash 4 bit ECC register 2 NAND4BITECC2 is shown in Figure 18 47 and described in Table 18 65 Figure 18 47 NAND Flash 4 Bit ECC Register 2 NAND4B...

Page 778: ...ue Description 31 26 Reserved 0 Reserved 25 16 4BITECCVAL6 0 3FFh Calculated 4 bit ECC or Syndrom Value6 15 10 Reserved 0 Reserved 9 0 4BITECCVAL5 0 3FFh Calculated 4 bit ECC or Syndrom Value5 18 4 19 NAND Flash 4 Bit ECC Register 4 NAND4BITECC4 The NAND Flash 4 bit ECC register 4 NAND4BITECC4 is shown in Figure 18 49 and described in Table 18 67 Figure 18 49 NAND Flash 4 Bit ECC Register 4 NAND4B...

Page 779: ... Description 31 26 Reserved 0 Reserved 25 16 4BITECCERRADD2 0 3FFh Calculated 4 bit ECC Error Address 2 15 10 Reserved 0 Reserved 9 0 4BITECCERRADD1 0 3FFh Calculated 4 bit ECC Error Address 1 18 4 21 NAND Flash 4 Bit ECC Error Address Register 2 NANDERRADD2 The NAND Flash 4 bit ECC error register 2 NANDERRADD2 is shown in Figure 18 51and described in Table 18 69 Figure 18 51 NAND Flash 4 Bit ECC ...

Page 780: ...alue Description 31 26 Reserved 0 Reserved 25 16 4BITECCERRVAL2 0 3FFh Calculated 4 bit ECC Error Value 2 15 10 Reserved 0 Reserved 9 0 4BITECCERRVAL1 0 3FFh Calculated 4 bit ECC Error Value 1 18 4 23 NAND Flash 4 Bit ECC Error Value Register 2 NANDERRVAL2 The NAND Flash 4 bit ECC error value register 2 NANDERRVAL2 is shown in Figure 18 53 and described in Table 18 71 Figure 18 53 NAND Flash 4 Bit...

Page 781: ...ruments Incorporated External Memory Interface B EMIFB Chapter 19 SPRUH91D March 2013 Revised September 2016 External Memory Interface B EMIFB This chapter describes the external memory interface B EMIFB Topic Page 19 1 Introduction 782 19 2 Architecture 783 19 3 Example Configuration 805 19 4 Registers 809 ...

Page 782: ... for the CPU to connect to a variety of external devices including Single data rate SDR SDRAM mobile SDR SDRAM 19 1 2 Features For details on features of EMIFB see your device specific data manual 19 1 3 Functional Block Diagram Figure 19 1 illustrates a high level view of the EMIFB and its connections within the device Multiple requesters have access to EMIFB through a switched central resource i...

Page 783: ...ails on the EMIFB s internal arbitration between performing requests and performing auto refresh cycles see Section 19 2 6 6 For further details regarding master prioritization within the EMIFB command FIFO see Section 19 2 6 11 19 2 3 Pin Descriptions Table 19 1 describes the function of each EMIFB pin Table 19 1 EMIF Pins Used to Access SDRAM Pins s I O Description EMB_D x 0 I O EMIFB data bus T...

Page 784: ...SDRAM commands described in Table 19 2 Table 19 3 shows the truth table for the SDRAM commands and an example timing waveform of the PRE command is shown in Figure 19 2 EMB_A 10 is pulled low in this example to deactivate only the bank specified by the EMB_BA pins Table 19 2 EMIF SDRAM Commands Command Function PRE Precharge Depending on the value of EMB_A 10 the PRE command either deactivates the...

Page 785: ... Truth Table for SDRAM Commands SDRAM Pins CKE CS RAS CAS WE BA 1 0 A 12 11 A 10 A 9 0 EMIFB Pins EMB_SDCKE EMB_CS EMB_RAS EMB_CAS EMB_WE EMB_BA 1 0 EMB_A 12 11 EMB_A 10 EMB_A 9 0 PRE H L L H L Bank X X L H X ACTV H L L H H Bank Row Row Row READ H L H L H Bank Column L Column WRT H L H L L Bank Column L Column BT H L H H L X X X X LMR H L L L L X Mode Mode Mode REFR H L L L H X X X X SLFR L L L L ...

Page 786: ...teristics Pre charge bit is A 10 The number of column address bits is 8 9 10 or 11 The number of row address bits is 13 in case of mobile SDR number of row address bits can be 9 10 11 12 or 13 The number of internal banks is 1 2 or 4 Figure 19 3 shows an interface between the EMIFB and a 2M 16 4 bank SDRAM device In addition Figure 19 4 shows an interface between the EMIFB and a 2M 32 4 bank SDRAM...

Page 787: ...mit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface B EMIFB Figure 19 5 EMIFB to Dual 4M 16 4 bank SDRAM Interface Table 19 4 Example of 32 bit EMIFB Address Pin Connections SDRAM Size Width Banks Address Pins 64M bits 16 4 SDRAM A 11 0 EMIFB EMB_A 11 0 32 4 SDRAM A 10 0 EMIFB EMB_A 10 0 128M bits 16 4 SDRAM A 11 0 EMIFB EMB_A 11 0 32 4 SDRAM A 1...

Page 788: ...et to 1 to enable mobile SDR This bit is writeable only when the BOOT_UNLOCK bit is unlocked BOOT_UNLOCK Boot Unlock Set to 1 to change the values of the fields that are affected by the BOOT_UNLOCK bit SDREN SDR Enable This bit enables EMIFB to interface to SDRAM type memories This bit is set to 1 by default TIMUNLOCK Timing Unlock Controls the write permission settings for the SDRAM timing 1 regi...

Page 789: ...ols the rate at which attached SDRAM devices will be refreshed The following equation can be used to determine the required value of REFRESH_RATE for an SDRAM device REFRESH_RATE EMIFB clock rate Required SDRAM Refresh Rate More information about the operation of the SDRAM refresh controller can be found in Section 19 2 6 6 Table 19 8 Description of the SDRAM Timing 1 Register SDTIM1 Parameter Des...

Page 790: ...SDRAM banks are open the EMIFB issues a PRE command with EMB_A 10 held high to indicate all banks This is done so that the maximum ACTV to PRE timing for an SDRAM is not violated 3 The EMIFB drives EMB_SDCKE high and begins continuously issuing NOP commands until eight SDRAM refresh intervals have elapsed An SDRAM refresh interval is equal to the value of the REFRESH_RATE field of the SDRAM refres...

Page 791: ...data manual 3 Enable SDR mode of the EMIFB by writing 1 to the SDREN bit write 1 to both SDREN and MSDRAM_ENABLE to enable mobile SDR in the SDRAM configuration register SDCFG Also ensure that pin multiplexing is properly configured 4 Program SDTIM1 and SDTIM2 to satisfy the timing requirements for the attached SDRAM device Take the timing parameters from the SDRAM datasheet 5 Program the REFRESH_...

Page 792: ...equests pending and none of the SDRAM banks are open Refresh Release 4 7 An auto refresh cycle is performed if the EMIFB has no requests pending regardless of whether any SDRAM banks are open Refresh Need 8 11 An auto refresh cycle is performed at the completion of the current access unless there are read requests pending Refresh Must 12 15 Multiple auto refresh cycles are performed at the complet...

Page 793: ...utes the requests after which it again goes back to self refresh state driving EMB_SDCKE low To use Partial Array Self Refresh for mobile SDR PASR bits in the SDRAM configuration 2 register must be appropriately programmed The EMIFB performs bank interleaving Since the SDRAM is partially refreshed during Partial Array Self Refresh it is the responsibility of software to move critical data into the...

Page 794: ... Bitfield in SDRAM Configuration 2 Register SDCFG2 Configuration you may select either 4 2 1 1 2 or 1 4 bank s The PASR bits are loaded into the extended mode register of the mobile SDR device during autoinitialization see Section 19 2 6 4 The EMIFB performs bank interleaving when the internal bank position IBANKPOS bit in SDRAM configuration register SDCFG is cleared to 0 Since the SDRAM banks ar...

Page 795: ...ion register SDCFG to 0 a burst size of four is used When configured to 16 bit by setting NM to 1 a burst size of eight is used Figure 19 6 shows a burst size of four Figure 19 6 Timing Waveform for Basic SDRAM Read Operation The EMIFB will truncate a series of bursting data if the remaining addresses of the burst are not required to complete the request The EMIFB can truncate the burst in three w...

Page 796: ...t size of four is used When configured to 16 bit by setting NM to 1 a burst size of eight is used Figure 19 7 shows a burst size of four Figure 19 7 Timing Waveform for Basic SDRAM Write Operation The EMIFB will truncate a series of bursting data if the remaining addresses of the burst are not part of the write request The EMIFB can truncate the burst in three ways By issuing another WRT to the sa...

Page 797: ...ytes or entire words The EMB_WE_DQM pins are always low during a READ command When using mobile SDRAM set IBANK_POS 1 and this uses an addressing scheme as described in Table 19 16 See device data manual to know possible values of ROWSIZE IBANK and PAGESIZE for EMIFB configured to interface with mobile SDRAM device When the IBANK_POS bit is set to 1 the PAGESIZE ROWSIZE and IBANK fields control th...

Page 798: ...E_DQM 1 0 32 1 2 Row Address BA 0 Column Address WE_DQM 1 0 64 2 2 Row Address BA 1 0 Column Address WE_DQM 1 0 32 0 3 Row Address Column Address WE_DQM 1 0 64 1 3 Row Address BA 0 Column Address WE_DQM 1 0 128 2 3 Row Address BA 1 0 Column Address WE_DQM 1 0 NOTE The upper bit of the Row Address is used only when addressing 256 Mbit and 512 Mbit SDRAM memories Table 19 16 Example Mapping from Log...

Page 799: ...a write FIFO a read FIFO and command and data schedulers Table 19 17 describes the purpose of each FIFO Figure 19 8 shows the block diagram of the SDRAM memory controller FIFOs Commands write data and read data arrive at the SDRAM memory controller parallel to each other The same peripheral bus is used to write and read data from external memory as well as internal memory mapped registers Table 19...

Page 800: ...sters and performs the following reordering Among all pending reads selects reads to rows already open Among all pending writes selects writes to rows already open Selects the highest priority command from pending reads and writes to open rows If multiple commands have the highest priority then the SDRAM memory controller selects the oldest command The SDRAM memory controller may now have a final ...

Page 801: ...ommand 19 2 6 11 3 Possible Race Condition A race condition may exist when certain masters write data to the SDRAM memory controller For example if master A passes a software message via a buffer in SDRAM memory and does not wait for indication that the write completes when master B attempts to read the software message it may read stale data and therefore receive an incorrect message In order to ...

Page 802: ...9 shows the EMIFB memory controller reset diagram Table 19 18 Reset Sources Reset Signal Reset Source CHIP_RST Hardware device reset MOD_G_RST Power and sleep controller Figure 19 9 EMIFB Memory Controller Reset Block Diagram When the RESET pin on the device is asserted or a system reset is issued from Code Composer Studio EMIFB memory controller s behavior is same as CHIP_RST assertion In all the...

Page 803: ...it to 0 and setting the LP_MODE bit to 1 in the SDRAM refresh control register SDRFC If the external memory requires a continuous clock the EMIFB memory controller clock provided by PLL must not be turned off because this may result in data corruption See the following subsections for the proper procedures to follow when stopping the EMIFB memory controller clocks Figure 19 10 EMIFB Memory Control...

Page 804: ...LK Clear MCLKSTOP_EN bit in SDRFC to 0 Bring EMIFB out of self refresh mode Refer to Section 19 2 6 7 for details on self refresh mode LPSC Auto Sleep and Auto Wake Apart from disable and enable EMIFB memory controller can make use of auto sleep and auto wake facility Following describes the procedure to be followed to put EMIFB memory controller in auto sleep state EMIFB should be put to self ref...

Page 805: ...DTIM2 the EMIFB memory controller can be configured to meet the data sheet specification for JESD21 C compliant SDR SDRAM This section presents an example describing how to interface the EMIFB memory controller to a JESD21 C SDR SDRAM 64MB device The EMIFB memory controller is assumed to be operating at 133 MHz Hardware Configuration The following figures show how to connect the EMIFB memory contr...

Page 806: ... 1 0 A 12 0 LDQM DQ 15 0 SDRAM 4M x 16 x 4 Bank EMB_WE_DQM 1 UDQM EMB_WE_DQM 2 EMB_D 31 16 EMB_WE_DQM 3 CE CAS RAS WE CLK CKE BA 1 0 A 12 0 LDQM DQ 15 0 SDRAM 4M x 16 x 4 Bank UDQM Example Configuration www ti com 806 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface B EMIFB Figure 19 11 Connecting ...

Page 807: ...To select 4 internal SDR SDRAM banks PAGESIZE 1h To select 512 word page size Configuring SDRAM Refresh Control Register SDRFC The SDRAM refresh control register SDRFC configures the EMIFB memory controller to meet the refresh requirements of the attached SDRAM device SDRFC also allows the EMIFB memory controller to enter and exit self refresh and power down and enable and disable the MCLK stoppin...

Page 808: ...r more information Table 19 21 SDTIM1 Configuration Register Field Name SDRAM Data Manual Parameter Name Description Data Manual Value ns Formula Register field must be Register Value T_RFC tRFC refresh cycle time 66 tRFC fEMB_CLK 1 8 T_RP tRP precharge command to refresh or activate command 20 tRP fEMB_CLK 1 2 T_RCD tRCD activate command to read write command 20 tRCD fEMB_CLK 1 2 T_WR tWR write r...

Page 809: ...sh Control Register Section 19 4 2 10h SDTIM1 SDRAM Timing 1 Register Section 19 4 3 14h SDTIM2 SDRAM Timing 2 Register Section 19 4 4 1Ch SDCFG2 SDRAM Configuration 2 Register SDRAM Configuration 2 Register SDCFG2 20h BPRIO Peripheral Bus Burst Priority Register Section 19 4 5 40h PC1 Performance Counter 1 Register Section 19 4 6 44h PC2 Performance Counter 2 Register Section 19 4 7 48h PCC Perfo...

Page 810: ...s NOTE Writing to the lower two bytes of this register will cause the EMIF to start the SDRAM initialization sequence Figure 19 14 SDRAM Configuration Register SDCFG 31 27 26 25 24 Reserved IBANK_POS MSDRAM_ENABLE Reserved R 0 R W 0 R W 0 R 0 23 22 17 16 BOOT_UNLOCK Reserved SDREN R W 0 R 0 R W 1 15 14 13 12 11 9 8 TIMUNLOCK NM Reserved CL Reserved R W 0 R W 0 R 0 R W 3h R 0 7 6 4 3 2 0 Reserved I...

Page 811: ...e SDRAM data bus width A write to this field will cause the EMIFB to start the SDRAM initialization sequence 0 32 bit SDR SDRAM 1 16 bit SDR SDRAM 13 12 Reserved 0 All writes to these bit s must always have a value of 0 11 9 CL 0 7h CAS Latency The value of this field defines the CAS latency to be used when accessing connected SDRAM devices A write to this field will cause the EMIFB to start the S...

Page 812: ...will cause connected SDRAM devices to be place into self refresh mode and the EMIFB to enter the self refresh state 0 SDRAM is not to be placed in self refresh power down mode 1 SDRAM placed in self refresh power down mode depending on the value of SR_PD bit 30 MCLKSTOP_EN mclk Stop Enable Writing a 1 to this bit enables mclk stopping 0 mclk stopping disabled 1 mclk stopping enabled 29 24 Reserved...

Page 813: ...refresh or activate command minus 1 Corresponds to the trp AC timing parameter in the SDRAM data sheet Calculate by T_RP trp EMB_CLK 1 21 19 T_RCD 0 7h Specifies the minimum number of EMB_CLK cycles from an activate command to a read or write command minus 1 Corresponds to the trcd AC timing parameter in the SDRAM data sheet Calculate by T_RCD trcd EMB_CLK 1 18 16 T_WR 0 7h Specifies the minimum n...

Page 814: ...g 2 Register SDTIM2 31 30 27 26 23 22 16 Rsvd T_RAS_MAX Reserved T_XSR R 0 R W Eh R 0 R W Ah 15 5 4 0 Reserved T_CKE R W 0 R W 7h LEGEND R W Read Write R Read only n value after reset Table 19 28 SDRAM Timing 2 Register SDTIM2 Field Descriptions Bit Field Value Description 31 Reserved 0 All writes to these bit s must always have a value of 0 30 27 T_RAS_MAX 0 Fh Maximum number of refresh_rate inte...

Page 815: ...resh These bits get loaded into the Extended Mode Register of a mobile SDRAM during initialization A write to this field will cause the EMIFB to start the SDRAM initialization sequence 0 4 banks will be refreshed 1h 2 banks will be refreshed 2h 1 bank will be refreshed 3h 4h Reserved 5h 1 2 bank will be refreshed 6h 1 4 bank will be refreshed 7h Reserved 15 3 Reserved 0 All writes to these bit s m...

Page 816: ...utilization of the SDRAM However it could lead to excessive blocking of high priority masters If the PRIO_RAISE bits are cleared to 00h then the EMIFB controller always honors the master priority regardless of open row bank status For most systems the BPRIO should be set to a moderately low value to provide an acceptable balance of SDRAM efficiency and latency for high priority masters for example...

Page 817: ...eep Controller PSC chapter The performance counter 1 register PC1 is shown in Figure 19 20 and described in Table 19 31 Figure 19 20 Performance Counter 1 Register PC1 31 0 Counter1 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 31 Performance Counter 1 Register PC1 Field Descriptions Bit Field Value Description 31 0 Counter1 0 FFFF FFFFh 32 bit counter that can be configured a...

Page 818: ...umber of accesses SDRAM EMIFB memory mapped register accesses The REGION_SEL2 bit field value in the performance counter master region select register PCMRS is a don t care 1 Chip select filter is enabled If the REGION_SEL2 bit field value in the performance counter master region select register PCMRS is REGION_SEL2 0 PC2 counts accesses to SDRAM memory REGION_SEL2 7h PC2 counts accesses to EMIFB ...

Page 819: ...are equal to the transfer size of data written to the DDR2 memory controller divided by the DBS 4h 0 0 Counts the number of external memory controller cycles EMB_CLK cycles that the command FIFO is full Use the following to calculate the counter value as a percentage counter value total EMB_CLK cycles in a sample period As the value of this counter approaches 100 the EMIFB memory controller is app...

Page 820: ...escription 31 24 MST_ID2 0 FFh Master ID for performance counter 2 register PC2 For the Master ID value for master peripherals in the device see the System Configuration SYSCFG Module chapter 23 20 Reserved 0 Any writes to these bit s must always have a value of 0 19 16 REGION_SEL2 0 Fh Region select for performance counter 2 register PC2 0 PC2 counts total SDRAM accesses 1h 6h Reserved 7h PC2 cou...

Page 821: ...us of the interrupt If the interrupt condition occurs the corresponding bit in IRR is set independent of whether or not the interrupt is enabled The IRR is shown in Figure 19 25 and described in Table 19 37 Figure 19 25 Interrupt Raw Register IRR 31 8 Reserved R 0 7 3 2 1 0 Reserved LT Reserved R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 37 Interrupt Raw Register I...

Page 822: ...terrupt Mask Register IMR 31 8 Reserved R 0 7 3 2 1 0 Reserved LTM Reserved R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 38 Interrupt Mask Register IMR Field Descriptions Bit Field Value Description 31 3 Reserved 0 All writes to these bit s must always have a value of 0 2 LTM Masked Line Trap Set to 1 by hardware to indicate illegal memory access type only if the LT...

Page 823: ...same time Writing a 0 has no effect 0 Line trap interrupt is not enabled a write of 1 to the LTMCLR bit in IMCR occurred 1 Line trap interrupt is enabled 1 0 Reserved 0 All writes to these bit s must always have a value of 0 19 4 13 Interrupt Mask Clear Register IMCR The interrupt mask clear register IMCR disables the memory controller interrupt Once an interrupt is enabled it may be disabled by w...

Page 824: ... GPIO The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an output you can write to an internal register to control the state driven on the output pin When configured as an input you can detect the state of the input by reading the state of an internal register This chapter describes the GPIO Topic Page 20 1 Introductio...

Page 825: ... through separate data set and clear registers allows multiple software processes to control GPIO signals without critical section protection Set clear functionality through writing to a single output data register is also supported Separate input output registers Output register can be read to reflect output drive status Input register can be read to reflect pin status All GPIO signals can be use...

Page 826: ...d of the GPIO peripheral is limited by system level latencies More specifically how quickly the GPIO registers can be written to or read from 20 2 2 Signal Descriptions The number of GPIO signals supported will vary between devices For information on the number of signals supported and the package pinout of each GPIO signal see your device specific data manual 20 2 3 Pin Multiplexing Extensive pin...

Page 827: ... GPIO pins additional control registers and fields should be appended using the same numbering scheme in the table Detailed information regarding the specific register names for each bank and the contents and function of these registers is presented in Section 20 3 Table 20 1 GPIO Register Bits and Banks Associated With GPIO Signals GPIO Pin Number GPIO Signal Name Bank Number Control Registers Re...

Page 828: ...3 Bit 14 GP2P14 48 GP2 15 2 register_name23 Bit 15 GP2P15 49 GP3 0 3 register_name23 Bit 16 GP3P0 50 GP3 1 3 register_name23 Bit 17 GP3P1 51 GP3 2 3 register_name23 Bit 18 GP3P2 52 GP3 3 3 register_name23 Bit 19 GP3P3 53 GP3 4 3 register_name23 Bit 20 GP3P4 54 GP3 5 3 register_name23 Bit 21 GP3P5 55 GP3 6 3 register_name23 Bit 22 GP3P6 56 GP3 7 3 register_name23 Bit 23 GP3P7 57 GP3 8 3 register_na...

Page 829: ...9 GP5P13 95 GP5 14 5 register_name45 Bit 30 GP5P14 96 GP5 15 5 register_name45 Bit 31 GP5P15 97 GP6 0 6 register_name67 Bit 0 GP6P0 98 GP6 1 6 register_name67 Bit 1 GP6P1 99 GP6 2 6 register_name67 Bit 2 GP6P2 100 GP6 3 6 register_name67 Bit 3 GP6P3 101 GP6 4 6 register_name67 Bit 4 GP6P4 102 GP6 5 6 register_name67 Bit 5 GP6P5 103 GP6 6 6 register_name67 Bit 6 GP6P6 104 GP6 7 6 register_name67 Bi...

Page 830: ...3 GP8 14 8 register_name8 Bit 14 GP8P14 144 GP8 15 8 register_name8 Bit 15 GP8P15 20 2 6 Using a GPIO Signal as an Output GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO direction register DIR This section describes using the GPIO signal as an output signal 20 2 6 1 Configuring a GPIO Output Signal To configure a given GPIO signal as an outp...

Page 831: ...ing a GPIO Signal as an Input GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO direction register DIR This section describes using the GPIO signal as an input signal 20 2 7 1 Configuring a GPIO Input Signal To configure a given GPIO signal as an input set the bit in DIR that is associated with the desired GPIO signal For detailed information ...

Page 832: ... of 16 by setting the appropriate bit s in the GPIO interrupt per bank enable register BINTEN For example to enable bank 0 interrupts events from GP0 15 0 set bit 0 in BINTEN to enable bank 3 interrupts events from GP3 15 0 set bit 3 in BINTEN For detailed information on BINTEN see Section 20 3 20 2 10 3 Configuring GPIO Interrupt Edge Triggering Each GPIO interrupt source can be configured to gen...

Page 833: ...ed interrupt flag in the CPU For the GPIO bank interrupts INTSTAT can be used to determine which GPIO interrupt occurred It is the responsibility of software to ensure that all pending GPIO interrupts are appropriately serviced Pending GPIO interrupt flags can be cleared by writing a logic 1 to the associated bit position in INTSTAT For detailed information on INTSTAT see Section 20 3 20 2 10 5 In...

Page 834: ...r Section 20 3 10 30h CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register Section 20 3 11 34h INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register Section 20 3 12 GPIO Banks 2 and 3 38h DIR23 GPIO Banks 2 and 3 Direction Register Section 20 3 3 3Ch OUT_DATA23 GPIO Banks 2 and 3 Output Data Register Section 20 3 4 40h SET_DATA23 GPIO Banks 2 and 3 Set Data Register Section 20 ...

Page 835: ...3 11 ACh INTSTAT67 GPIO Banks 6 and 7 Interrupt Status Register Section 20 3 12 GPIO Bank 8 B0h DIR8 GPIO Bank 8 Direction Register Section 20 3 3 B4h OUT_DATA8 GPIO Bank 8 Output Data Register Section 20 3 4 B8h SET_DATA8 GPIO Bank 8 Set Data Register Section 20 3 5 BCh CLR_DATA8 GPIO Bank 8 Clear Data Register Section 20 3 6 C0h IN_DATA8 GPIO Bank 8 Input Data Register Section 20 3 7 C4h SET_RIS...

Page 836: ...isable or enable the bank 7 interrupts events from GP7 15 0 0 Bank 7 interrupts are disabled 1 Bank 7 interrupts are enabled 6 EN6 Bank 6 interrupt enable is used to disable or enable the bank 6 interrupts events from GP6 15 0 0 Bank 6 interrupts are disabled 1 Bank 6 interrupts are enabled 5 EN5 Bank 5 interrupt enable is used to disable or enable the bank 5 interrupts events from GP5 15 0 0 Bank...

Page 837: ...P0P2 GP0P1 GP0P0 R W 1 LEGEND R W Read Write n value after reset Figure 20 5 GPIO Banks 2 and 3 Direction Register DIR23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 GP2P4 GP2P3 G...

Page 838: ...ed R W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 1 LEGEND R W Read Write n value after reset Table 20 5 GPIO Direction Register DIRn Field Descriptions Bit Field Value Description 31 0 GPkPj Direction of pin GPk j The GPkPj bit is used to control the direction output 0 input 1 of pin j in GPIO b...

Page 839: ...11 10 9 8 7 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 10 GPIO Banks 2 and 3 Output Data Register OUT_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 1...

Page 840: ...7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 6 GPIO Output Data Register OUT_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Output drive state of GPk j The GPkPj bit is used to drive the output low 0 high 1 of pin j in GPIO bankk The GPkPj bit is ignore...

Page 841: ... 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 15 GPIO Banks 2 and 3 Set Data Register SET_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 ...

Page 842: ...8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 7 GPIO Set Data Register SET_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Set the output drive state of GPk j to logic high The GPkPj bit is used to drive the output high on pin j in GPIO bankk The GPkPj bit is ignored when GPk j is configured a...

Page 843: ... 7 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 20 GPIO Banks 2 and 3 Clear Data Register CLR_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11...

Page 844: ...8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 8 GPIO Clear Data Register CLR_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Clear the output drive state of GPk j to logic low The GPkPj bit is used to drive the output low on pin j in GPIO bankk The GPkPj bit is ignored when GPk j is configured...

Page 845: ...P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R 0 LEGEND R Read only n value after reset Figure 20 25 GPIO Banks 2 and 3 Input Data Register IN_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P...

Page 846: ...TA8 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R 0 LEGEND R Read only n value after reset Table 20 9 GPIO Input Data Register IN_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Status of pin GPk j Reading the GPkPj bit returns the state of pin j in GPIO bank k 0 GPk j...

Page 847: ... GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 30 GPIO Banks 2 and 3 Set Rise Trigger Register SET_RIS_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 ...

Page 848: ...R W 0 LEGEND R W Read Write n value after reset Table 20 10 GPIO Set Rising Edge Trigger Interrupt Register SET_RIS_TRIGn Field Descriptions Bit Field Value Description 31 0 GPjPk Enable rising edge trigger interrupt detection on GPk j Reading the GPkPj bit in either SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt generation function is enabled for ...

Page 849: ...0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 35 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_RIS_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 G...

Page 850: ...1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 11 GPIO Clear Rising Edge Interrupt Register CLR_RIS_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Disable rising edge interrupt detection on GPk j Reading the GPkPj bit in either SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt generation function is enabled for GPk j...

Page 851: ...0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 40 GPIO Banks 2 and 3 Set Rise Trigger Register SET_FAL_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2...

Page 852: ...W 0 LEGEND R W Read Write n value after reset Table 20 12 GPIO Set Falling Edge Trigger Interrupt Register SET_FAL_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Enable falling edge trigger interrupt detection on GPk j Reading the GPkPj bit in either SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function is enabled for...

Page 853: ...GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 45 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_FAL_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6...

Page 854: ...GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 13 GPIO Clear Falling Edge Interrupt Register CLR_FAL_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Disable falling edge interrupt detection on GPk j Reading the GPkPj bit in either SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function is enabled for GPk ...

Page 855: ...bit writing 0 has no effect n value after reset Figure 20 50 GPIO Banks 2 and 3 Interrupt Status Register INTSTAT23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W1C 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 GP2P4 GP2P3 GP2P...

Page 856: ...12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W1C 0 LEGEND R W Read Write W1C Write 1 to clear bit writing 0 has no effect n value after reset Table 20 14 GPIO Interrupt Status Register INTSTATn Field Descriptions Bit Field Value Description 31 0 GPkPj Interrupt status of GPk j The GPkPj bit is used to monitor pending GPIO interrupts on pin j of GPIO bank k Write a...

Page 857: ... Copyright 2013 2016 Texas Instruments Incorporated Host Port Interface HPI Chapter 21 SPRUH91D March 2013 Revised September 2016 Host Port Interface HPI This chapter describes the host port interface HPI Topic Page 21 1 Introduction 858 21 2 Architecture 861 21 3 Registers 881 ...

Page 858: ...r the host can also use the HPI to bootload the processor by downloading program and data information to the processor s memory after power up 21 1 2 Features The HPI supports the following features Multiplexed address data Dual 16 bit halfword cycle access internal data word is 32 bits wide 16 bit wide host data bus interface Internal data bursting using 8 word read and write first in first out F...

Page 859: ... host cycle consists of two consecutive 16 bit transfers When the host drives an address on the bus the address is stored in a 32 bit address register HPIA in the HPI so that the bus can then be used for data The HPI contains two address registers HPIAR and HPIAW which can be used as separate address registers for read accesses and write accesses for details see Section 21 2 6 1 A control register...

Page 860: ...an international organization It is a generic parallel interface that can be configured to gluelessly interface to a variety of parallel devices 21 1 5 Terminology Used in This Document The following is a brief explanation of some terms used in this document Term Meaning CPU DSP CPU host External host device HPI DMA logic Logic used to communicate between the HPI and the DMA system that moves data...

Page 861: ...dicates the transfer is a read from the HPI while driving UHPI_HR W low indicates a write to the HPI UHPI_HHWIL I Address or control pins Halfword identification line The host uses UHPI_HHWIL to identify the first and second halfwords of the host cycle UHPI_HHWIL must be driven low for the first halfword and high for the second halfword UHPI_HAS I None Address strobe Connect to logic high UHPI_HIN...

Page 862: ... GPIO Enable Bit s When Enabled as GPIO Treated as Driven UHPI_HD 15 8 GPIOEN8 0 UHPI_HD 7 0 GPIOEN7 0 UHPI_HCNTL0 GPIOEN1 1 UHPI_HCNTL1 GPIOEN1 1 UHPI_HAS GPIOEN2 1 21 2 4 2 General Purpose I O Programmer s Model For each HPI pin there are three bits that control this pin as general purpose I O GPIO Enable GPIO_EN GPIOEN xx Direction GPIO_DIRn DIR yy Data GPIO_DATn DIR yy For example the UHPI_HAS...

Page 863: ...interact with the two HPI address registers Using the DUALHPIA bit in the HPI control register HPIC the host determines whether HPIAR and HPIAW act as a single 32 bit register single HPIA mode or as two independent 32 bit registers dual HPIA mode Note that the addresses loaded into the HPI address registers must be byte addresses and must be 32 bit word aligned with the least significant two bits ...

Page 864: ...hile HPIASEL 1 only HPIAR is read or updated by the host While HPIASEL 0 only HPIAW is read or updated by the host The HPIASEL bit is only meaningful in the dual HPIA mode NOTE The HPIASEL bit does not affect the HPI DMA logic Regardless of the value of HPIASEL the HPI DMA logic uses HPIAR when reading from memory and HPIAW when writing to memory A host HPID access with autoincrementing UHPI_HCNTL...

Page 865: ...n HPI resources are temporarily busy or unavailable the HPI can communicate this to the host by deasserting the HPI ready UHPI_HRDY output signal When performing an access the HPI first latches the levels on UHPI_HCNTL 1 0 UHPI_HR W and other control signals This latching can occur on the falling edge of the internal strobe signal for details see Section 21 2 6 4 After the control information is l...

Page 866: ..._HDS strobe input can be tied together and driven with a single strobe signal from the host This technique selects the HPI and provides the strobe simultaneously When using this method be aware that UHPI_HRDY is gated by UHPI_HCS as previously described It is not recommended to tie both UHPI_HDS1 and UHPI_HDS2 to static logic levels and use UHPI_HCS as a strobe 1 The UHPI_HR W signal could be driv...

Page 867: ... With the UHPI_HCNTL and UHPI_HR W Signals UHPI_HCNTL1 UHPI_HCNTL0 UHPI_HR W Cycle Type 0 0 0 HPIC write cycle 0 0 1 HPIC read cycle 0 1 0 HPID write cycle with autoincrementing 0 1 1 HPID read cycle with autoincrementing 1 0 0 HPIA write cycle 1 0 1 HPIA read cycle 1 1 0 HPID write cycle without autoincrementing 1 1 1 HPID read cycle without autoincrementing 21 2 6 6 UHPI_HHWIL Identifying the Fi...

Page 868: ... accessed regardless of whether the host performs a single or dual access For an example timing diagram of this case see Section 21 2 6 8 21 2 6 7 Performing a Multiplexed Access Figure 21 2 shows an example of signal connections for multiplexed transfers Figure 21 4 and Figure 21 5 show typical HPI signal activity when performing a read and write transfer respectively In these cases the falling e...

Page 869: ... SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Host Port Interface HPI Figure 21 5 Multiplexed Mode Host Write Cycle NOTE Depending on the type of write operation HPID without autoincrementing HPIA HPIC or HPID with autoincrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur For more informat...

Page 870: ...ates These wait states indicate to the host that read data is not yet valid read cycle or that the HPI is not ready to latch write data write cycle The number of wait states that must be inserted by the HPI is dependent upon the state of the resource that is being accessed When the HPI is not ready to complete the current cycle UHPI_HRDY is high the host can begin a new host cycle by forcing the H...

Page 871: ...lfword access is performed the same register will be accessed twice Figure 21 7 UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode Figure 21 8 includes an HPID read cycle without autoincrementing The host writes the memory address during the HPIA UHPI_HCNTL 1 0 10b write cycle and the host reads the data during the HPID UHPI_HCNTL 1 0 11b read cycle UHPI_HRDY goes high fo...

Page 872: ...HRDY to go high and the state of UHPI_HHWIL is ignored Firmware is not required to perform a dual access to access HPIC Figure 21 10 UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode Figure 21 11 includes a HPID write cycle without autoincrementing The host writes the memory address while UHPI_HCNTL 1 0 10b and writes the data while UHPI_HCNTL 1 0 11b During the HPID write cycl...

Page 873: ...e 21 13 the write FIFO is not empty when the HPIA access is made UHPI_HRDY goes high twice for the first halfword access of the HPIA write cycle The first UHPI_HRDY high period is due to the nonempty FIFO The data currently in the FIFO must first be written to the memory This results in UHPI_HRDY going high immediately after the falling edge of the data strobe HSTRB The second and third UHPI_HRDY ...

Page 874: ...st in first out buffers FIFOs As shown in Figure 21 14 a read FIFO supports host read cycles and a write FIFO supports host write cycles Both read and write FIFOs are 8 words deep each word is 32 bits If the host is performing multiple reads or writes to consecutive memory addresses autoincrement HPID cycles the FIFOs are used for bursting The HPI DMA logic reads or writes a burst of four words at...

Page 875: ... an event that causes a read FIFO flush see Section 21 2 6 10 3 As mentioned the second way that read bursting may begin is with a FETCH command The host should always precede the FETCH command with the initialization of the HPIAR register or a nonautoincrement access so that the read FIFO is flushed beforehand When the host initiates a FETCH command the HPI DMA logic begins to prefetch data to ke...

Page 876: ... waiting in the FIFO the HPI holds off the host by deasserting UHPI_HRDY until at least one empty word location is available in the FIFO Because excessive time might pass between consecutive burst operations the HPI has a time out counter If there are fewer than four words in the write FIFO and the time out counter expires the HPI DMA logic empties the FIFO immediately by performing a 2 word or 3 ...

Page 877: ...cenarios cause both FIFOs to be flushed when DUALHPIA 0 The host performs a write to the HPIA register The host performs an HPID write cycle with autoincrementing while the read FIFO is not empty the read FIFO still contains data from prefetching or an HPID read cycle with autoincrementing The host performs an HPID read cycle with autoincrementing while the write FIFO is not empty there is still p...

Page 878: ...ly updated If the active cycle was a read cycle the fetched value may not be valid The HPI registers are reset to their default values see Section 21 3 The read and write FIFOs and the associated FIFO logic are reset this includes a flush of the FIFOs Host to CPU and CPU to host interrupts are cleared 21 2 8 Initialization The following steps are required to configure the HPI after a hardware rese...

Page 879: ...e 21 15 Figure 21 15 Host to CPU Interrupt State Diagram A When the DSPINT bit transitions from 0 to 1 an interrupt is generated to the CPU No new interrupt can be generated until the CPU has cleared the bit DSPINT 0 To interrupt the CPU the host must 1 Drive both UHPI_HCNTL1 and UHPI_HCNTL0 low to request a write to HPIC 2 Write 1 to the DSPINT bit in HPIC When the host sets the DSPINT bit the HP...

Page 880: ...edge the current interrupt by writing 1 to the HINT bit When the host does this the HPI clears the HINT bit HINT 0 and this drives the UHPI_HINT signal high The CPU should read HPIC and make sure HINT 0 before generating subsequent interrupts Writes of 0 have no effect A hardware reset immediately clears the HINT bit and thus clears an active CPU to host interrupt 21 2 10 EDMA Event Support The HP...

Page 881: ...urs UHPI_HRDY continues to be driven low holding off the host until the emulation suspend condition is over and the FIFOs are serviced by the HPI DMA logic allowing the host cycle to complete When the emulation suspend condition is over the appropriate requests by the HPI DMA logic are made to process any posted host writes in the write FIFO or to fill the read FIFO as necessary HPI operation then...

Page 882: ...ines the emulation mode of the HPI PWREMU_MGMT is shown in Figure 21 18 and described in Table 21 8 Figure 21 18 Power and Emulation Management Register PWREMU_MGMT 31 16 Reserved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 21 8 Power and Emulation Management Register PWREMU_MGMT Field Descriptions Bit Field Value Description 31 2 Res...

Page 883: ... 15 8 pins 0 Disable pins for GPIO Pins functions as HPI signal 1 Enable pins for GPIO 7 GPIOEN7 Enable as GPIO for UHPI_HD 7 0 pins 0 Disable pins for GPIO Pins functions as HPI signal 1 Enable pins for GPIO 6 GPIOEN6 Enable as GPIO for UHPI_HINT pin 0 Disable pin for GPIO Pin functions as HPI signal 1 Enable pin for GPIO 5 GPIOEN5 Enable as GPIO for UHPI_HRDY pin 0 Disable pin for GPIO Pin funct...

Page 884: ...n 0 UHPI_HDn pin is an input 1 UHPI_HDn pin is an output 21 3 5 GPIO Data 1 Register GPIO_DAT1 The GPIO data 1 register GPIO_DAT1 determines the value driven on the corresponding UHPI_HDn pin if the pin is configured as an output GPIO_DIR1 HDn 1 Writes do not affect pins not configured as GPIO outputs The bits in GPIO_DAT1 are set or cleared by writing directly to this register A read of GPIO_DAT1...

Page 885: ...ol for UHPI_HRDY pin 0 UHPI_HRDY pin is an input 1 UHPI_HRDY pin is an output 8 HINTZ Direction control for UHPI_HINT pin 0 UHPI_HINT pin is an input 1 UHPI_HINT pin is an output 7 HCNTL0 Direction control for UHPI_HCNTL0 pin 0 UHPI_HCNTL0 pin is an input 1 UHPI_HCNTL0 pin is an output 6 HCNTL1 Direction control for UHPI_HCNTL1 pin 0 UHPI_HCNTL1 pin is an input 1 UHPI_HCNTL1 pin is an output 5 HHW...

Page 886: ...GPIO Data 2 Register GPIO_DAT2 31 16 Reserved R 0 15 10 9 8 Reserved HRDY HINTZ R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 HCNTL0 HCNTL1 HHWIL HRW HDS2Z HDS1Z HCSZ HASZ R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 21 13 GPIO Data 2 Register GPIO_DAT2 Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 HRDY 0 1 Data read fro...

Page 887: ...errupt to the host Figure 21 24 Host Port Interface Control Register HPIC Host Access Permissions 31 16 Reserved R 0 15 12 11 10 9 8 Reserved HPIASEL Reserved DUALHPIA HWOBSTAT R 0 R W 0 R W 0 R W 0 R 0 7 6 5 4 3 2 1 0 HPIRST Reserved FETCH Reserved HINT DSPINT HWOB R 1 R 2h R W 0 R 1 R W 1 Host R W1C 0 CPU R W 0 R W 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect ...

Page 888: ...OB bit is logic 1 7 HPIRST HPI reset Some HPI logic is held in reset when the HPIRST bit is set The HPIRST bit must be cleared to 0 before data transactions can take place 0 HPI is released from reset 1 HPI is held in reset 6 5 Reserved 2h Reserved 4 FETCH Host data fetch request bit Only the host may write to FETCH When a host writes a 1 to FETCH a request is posted in the HPI to prefetch data in...

Page 889: ...nly n value after reset Table 21 15 Host Port Interface Write Address Register HPIAW Field Descriptions Bit Field Value Description 31 0 HPIAW 0 FFFF FFFFh Host port interface write address 21 3 10 Host Port Interface Read Address Register HPIAR The HPI contains two 32 bit address registers one for read operations HPIAR and one for write operations HPIAW The host port interface read address regist...

Page 890: ...Chapter 22 SPRUH91D March 2013 Revised September 2016 Inter Integrated Circuit I2C Module This chapter describes the inter integrated circuit I2C peripheral The scope of this chapter assumes that you are familiar with the Philips Semiconductors Inter IC bus I2C bus specification version 2 1 Topic Page 22 1 Introduction 891 22 2 Architecture 893 22 3 Registers 905 ...

Page 891: ...mpliance with the Philips Semiconductors I2C bus specification version 2 1 Support for byte format transfer 7 bit and 10 bit addressing modes General call START byte mode Support for multiple master transmitters and slave receivers mode Support for multiple slave transmitters and master receivers mode Combined master transmit receive and receive transmit mode I2C data transfer rate of from 10 kbps...

Page 892: ...16 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Inter Integrated Circuit I2C Module 22 1 3 Functional Block Diagram A block diagram of the I2C peripheral is shown in Figure 24 1 Refer to Section 22 2 for detailed information about the architecture of the I2C peripheral Figure 22 1 I2C Peripheral Block Diagram 22 1 4 Industry Standard s Compliance Statement The I...

Page 893: ... in the EDMA controller can be synchronized to data reception and data transmission in the I2C peripheral Figure 24 1 shows the four registers used for transmission and reception The CPU or the EDMA controller writes data for transmission to ICDXR and reads received data from ICDRR When the I2C peripheral is configured as a transmitter data written to ICDXR is copied to ICXSR and shifted out on th...

Page 894: ...clock The prescaled module clock must be operated within the range of 6 7 to 13 3 MHz The I2C clock dividers divide down the high ICCH bit in ICCLKH and low portions ICCL bit in ICCLKL of the prescaled module clock signal to produce the I2C serial clock which appears on the I2Cx_SCL pin when the I2C module is configured to be a master on the I2C bus The prescaler IPSC bit in ICPSC must only be ini...

Page 895: ...high period If a device pulls down the clock line for a longer time the result is that all clock generators must enter the wait state This way a slave slows down a fast master and the slow device creates enough time to store a received data word or to prepare a data word that you are going to transmit Figure 22 4 Synchronization of Two I2C Clock Generators During Arbitration 22 2 4 Signal Descript...

Page 896: ...ition on the I2Cx_SDA line while I2Cx_SCL is high A master drives this condition to indicate the start of a data transfer The STOP condition is defined as a low to high transition on the I2Cx_SDA line while I2Cx_SCL is high A master drives this condition to indicate the end of a data transfer The I2C bus is considered busy after a START condition and before a subsequent STOP condition The bus busy...

Page 897: ... data values being transferred The I2C peripheral supports the following data formats 7 bit addressing mode 10 bit addressing mode Free data format mode Figure 22 7 I2C Peripheral Data Transfer 22 2 6 1 7 Bit Addressing Format In the 7 bit addressing format Figure 22 8 the first byte after a START condition S consists of a 7 bit slave address followed by a R W bit The R W bit determines the direct...

Page 898: ...g to Slave Receiver FDF 0 XA 1 in ICMDR n The number of data bits from 1 to 8 specified by the bit count BC field of ICMDR 22 2 6 3 Free Data Format In the free data format Figure 22 10 the first bits after a START condition S are a data word An ACK bit is inserted after each data word The data word can be from 1 to 8 bits depending on the bit count BC bits of ICMDR No address or data direction bi...

Page 899: ... master This mode can only be entered from the slave receiver mode the I2C peripheral must first receive a command from the master When you are using any of the 7 bit 10 bit addressing formats the I2C peripheral enters its slave transmitter mode if the slave address is the same as its own address in ICOAR and the master has transmitted R W 1 As a slave transmitter the I2C peripheral then shifts th...

Page 900: ...n Basic Optional Slave receiver mode Disable data transfers STT 0 in ICSTR Allow an overrun condition RSFULL 1 in ICSTR Reset the peripheral IRS 0 in ICMDR Set the NACKMOD bit of ICMDR before the rising edge of the last data bit you intend to receive Master receiver mode AND Repeat mode RM 1 in ICMDR Generate a STOP condition STOP 1 in ICMDR Reset the peripheral IRS 0 in ICMDR Set the NACKMOD bit ...

Page 901: ...master transmitter that drives I2Cx_SDA low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value Should two or more devices send identical first bytes arbitration continues on the subsequent bytes If the I2C peripheral is the losing master it switches to the slave receiver mode sets the arbitration lost AL flag and generates the ...

Page 902: ...e set to their default values and the I2C peripheral remains disabled until the I2C reset IRS bit in the I2C mode register ICMDR is changed to 1 NOTE The IRS bit must be cleared to 0 while you configure reconfigure the I2C peripheral Forcing IRS to 0 can be used to save power and to clear error conditions 22 2 11 Initialization Proper I2C initialization is required prior to starting communication ...

Page 903: ... is between 6 7 and 13 3 MHz 6 Configure I2C master clock frequency Configure the low time divider value ICCLKL Configure the high time divider value ICCLKH 7 Make sure the interrupt status register ICSTR is cleared Read ICSTR and write it back write 1 to clear ICSTR ICSTR Read ICIVR until it is 0 8 Take I2C controller out of reset enable I2C controller set IRS bit 1 in ICMDR 9 Wait until bus busy...

Page 904: ... Condition Detection interrupt SCD Generated when a STOP condition has been detected Address as Slave interrupt AAS Generated when the I2C has recognized its own slave address or an address of all 8 zeros 22 2 13 DMA Events Generated by the I2C Peripheral For the EDMA controller to handle transmit and receive data the I2C peripheral generates the following two EDMA events Activity in EDMA channels...

Page 905: ...vider Register Section 22 3 4 10h ICCLKH I2C Clock High Time Divider Register Section 22 3 4 14h ICCNT I2C Data Count Register Section 22 3 5 18h ICDRR I2C Data Receive Register Section 22 3 6 1Ch ICSAR I2C Slave Address Register Section 22 3 7 20h ICDXR I2C Data Transmit Register Section 22 3 8 24h ICMDR I2C Mode Register Section 22 3 9 28h ICIVR I2C Interrupt Vector Register Section 22 3 10 2Ch ...

Page 906: ...n in Figure 22 13 and described in Table 22 5 Figure 22 13 I2C Own Address Register ICOAR 31 16 Reserved R 0 15 10 9 0 Reserved OADDR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 5 I2C Own Address Register ICOAR Field Descriptions Bit Field Value Description 31 10 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effec...

Page 907: ...ription 31 7 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 6 AAS Address as slave interrupt enable bit 0 Interrupt request is disabled 1 Interrupt request is enabled 5 SCD Stop condition detected interrupt enable bit 0 Interrupt request is disabled 1 Interrupt request is enabled 4 ICXRDY Transmit data ready interrupt enable bit 0 Inter...

Page 908: ...affected is when the NACK mode is used see the description for NACKMOD in Section 22 3 9 0 NACK is not sent NACKSNT is cleared by one of the following events It is manually cleared To clear this bit write a 1 to it The I2C is reset either when 0 is written to the IRS bit of ICMDR or when the processor is reset 1 NACK is sent A no acknowledge bit was sent during the acknowledge cycle on the I2C bus...

Page 909: ...en detected 4 ICXRDY Transmit data ready interrupt flag bit ICXRDY indicates that the data transmit register ICDXR is ready to accept new data because the previous data has been copied from ICDXR to the transmit shift register ICXSR The CPU can poll ICXRDY or use the XRDY interrupt request 0 ICDXR is not ready ICXRDY is cleared by one of the following events Data is written to ICDXR ICXRDY is manu...

Page 910: ...eset 1 NACK bit is received The hardware detects that a no acknowledge NACK bit has been received Note While the I2C performs a general call transfer NACK is 1 even if one or more slaves send acknowledgment 0 AL Arbitration lost interrupt flag bit only applicable when the I2C is a master transmitter AL primarily indicates when the I2C has lost an arbitration contest with another master transmitter...

Page 911: ...ICCLKL Field Descriptions Bit Field Value Description 31 16 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 15 0 ICCL 0 FFFFh Clock low time divide down value of 1 65536 The period of the module clock is multiplied by ICCL d to produce the low time duration of the I2C serial on the I2Cx_SCL pin 22 3 4 2 I2C Clock High Time Divider Regist...

Page 912: ...ransfer with a STOP condition when the countdown is complete that is when the last data word has been transferred ICCNT is shown in Figure 22 18 and described in Table 22 10 Figure 22 18 I2C Data Count Register ICCNT 31 16 Reserved R 0 15 0 ICDC R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 10 I2C Data Count Register ICCNT Field Descriptions Bit Field Value Description 31 16...

Page 913: ...is selected by the bit count bits BC of ICMDR The I2C receive shift register ICRSR shifts in the received data from the I2Cx_SDA pin Once data is complete the I2C copies the contents of ICRSR into ICDRR The CPU and the EDMA controller cannot access ICRSR ICDRR is shown in Figure 22 19 and described in Table 22 11 Figure 22 19 I2C Data Receive Register ICDRR 31 16 Reserved R 0 15 8 7 0 Reserved D R...

Page 914: ...ICSAR are used bits 9 7 are ignored ICSAR is shown in Figure 22 20 and described in Table 22 12 Figure 22 20 I2C Slave Address Register ICSAR 31 16 Reserved R 0 15 10 9 0 Reserved SADDR R 0 R W 3FFh LEGEND R W Read Write R Read only n value after reset Table 22 12 I2C Slave Address Register ICSAR Field Descriptions Bit Field Value Description 31 10 Reserved 0 These reserved bit locations are alway...

Page 915: ...the bit count bits BC of ICMDR Once data is written to ICDXR the I2C copies the contents of ICDXR into the I2C transmit shift register ICXSR The ICXSR shifts out the transmit data from the I2Cx_SDA pin The CPU and the EDMA controller cannot access ICXSR ICDXR is shown in Figure 22 21 and described in Table 22 13 Figure 22 21 I2C Data Transmit Register ICDXR 31 16 Reserved R 0 15 8 7 0 Reserved D R...

Page 916: ...NACKMOD before the rising edge of the last data bit 14 FREE This emulation mode bit is used to determine the state of the I2C when a breakpoint is encountered in the high level language debugger 0 When I2C is master If I2Cx_SCL is low when the breakpoint occurs the I2C stops immediately and keeps driving I2Cx_SCL low whether the I2C is the transmitter or the receiver If I2Cx_SCL is high the I2C wa...

Page 917: ... bit is manually set to 1 regardless of the value in ICCNT 6 DLB Digital loopback mode bit only applicable when the I2C is a master transmitter This bit disables or enables the digital loopback mode of the I2C The effects of this bit are shown in Figure 22 23 Note that DLB mode in the free data format mode DLB 1 and FDF 1 is not supported 0 Digital loopback mode is disabled 1 Digital loopback mode...

Page 918: ...tion 0 0 0 None No activity 0 0 1 P STOP condition 0 1 0 S A D n D START condition slave address n data words n value in ICCNT 0 1 1 S A D n D P START condition slave address n data words STOP condition n value in ICCNT 1 0 0 None No activity 1 0 1 P STOP condition 1 1 0 S A D D D Repeat mode transfer START condition slave address continuous data transfers until STOP condition or next START condit...

Page 919: ...or EDMA From CPU or EDMA From CPU or EDMA From CPU or EDMA SCLn SDAn I2C peripheral DLB DLB www ti com Registers 919 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Inter Integrated Circuit I2C Module Figure 22 23 Block Diagram Showing the Effects of the Digital Loopback Mode DLB Bit ...

Page 920: ...n in Figure 22 24 and described in Table 22 17 Figure 22 24 I2C Interrupt Vector Register ICIVR 31 16 Reserved R 0 15 2 0 Reserved INTCODE R 0 R 0 LEGEND R Read only n value after reset Table 22 17 I2C Interrupt Vector Register ICIVR Field Descriptions Bit Field Value Description 31 3 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 2 0 I...

Page 921: ...scriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 IGNACK Ignore NACK mode 0 Master transmitter operates normally that is it discontinues the data transfer and sets the ARDY and NACK bits in ICSTR when receiving a NACK from the slave 1 Master transmitter ignores a NACK from the slave 0 BCM Backw...

Page 922: ...Changing the IPSC value while IRS 1 has no effect ICPSC is shown in Figure 22 26 and described in Table 22 19 Figure 22 26 I2C Prescaler Register ICPSC 31 16 Reserved R 0 15 8 7 0 Reserved IPSC R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 19 I2C Prescaler Register ICPSC Field Descriptions Bit Field Value Description 31 8 Reserved 0 These reserved bit locations are alway...

Page 923: ...h LEGEND R Read only n value after reset Table 22 20 I2C Revision Identification Register 1 REVID1 Field Descriptions Bit Field Value Description 31 0 REVID1 4415h Peripheral Identification Number 22 3 14 I2C Revision Identification Register REVID2 The I2C revision identification register REVID2 contains identification data for the peripheral REVID2 is shown in Figure 22 28 and described in Table ...

Page 924: ... R 0 15 1 0 Reserved TXDMAEN RXDMAEN R 0 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 22 22 I2C DMA Control Register ICDMAC Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 TXDMAEN Transmit DMA enable This bit controls the transmit DMA event pin to the system...

Page 925: ...C Pin Function Register ICPFUNC Field Descriptions Bit Field Value Description 31 1 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 0 PFUNC0 Controls the function of the I2Cx_SCL and I2Cx_SDA pins 0 Pins function as I2Cx_SCL and I2Cx_SDA 1 Pins function as GPIO Note No hardware protection is required to disable the I2C function when the ...

Page 926: ...gister ICPDIR 31 16 Reserved R 0 15 2 1 0 Reserved PDIR1 PDIR0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 24 I2C Pin Direction Register ICPDIR Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDIR1 Controls the direction of the I2Cx_SDA pin when conf...

Page 927: ...In Register ICPDIN 31 16 Reserved R 0 15 2 1 0 Reserved PDIN1 PDIN0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 25 I2C Pin Data In Register ICPDIN Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDIN1 Indicates the logic level present on the I2Cx_SDA...

Page 928: ...DOUT 31 16 Reserved R 0 15 2 1 0 Reserved PDOUT1 PDOUT0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 26 I2C Pin Data Out Register ICPDOUT Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDOUT1 Controls the level driven on the I2Cx_SDA pin when configu...

Page 929: ... 0 15 2 1 0 Reserved PDSET1 PDSET0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 27 I2C Pin Data Set Register ICPDSET Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDSET1 Used to set the PDOUT1 bit in the I2C pin data out register ICPDOUT that corres...

Page 930: ... 15 2 1 0 Reserved PDCLR1 PDCLR0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 28 I2C Pin Data Clear Register ICPDCLR Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDCLR1 Used to clear the PDOUT1 bit in the I2C pin data out register ICPDOUT that corr...

Page 931: ...r LCDC Chapter 23 SPRUH91D March 2013 Revised September 2016 Liquid Crystal Display Controller LCDC The liquid crystal display controller LCDC is capable of supporting an asynchronous memory mapped LCD interface and a synchronous raster type LCD interface This chapter describes the LCDC Topic Page 23 1 Introduction 932 23 2 Architecture 933 23 3 Registers 949 ...

Page 932: ...rts a wide variety of monochrome and full color display types and sizes by use of programmable timing controls a built in palette and a gray scale serializer Graphics data is processed and stored in frame buffers A frame buffer is a contiguous memory block in the system A built in DMA engine supplies the graphics data to the Raster engine which in turn outputs to the external LCD device The LIDD C...

Page 933: ...sed for each pixel In some documentation this is also referred to as color depth RGB Red Green Blue 23 2 Architecture 23 2 1 Clocking This section details the various clocks and signals Figure 23 2 shows input and output LCD controller clocks Figure 23 2 Input and Output Clocks 23 2 1 1 Pixel Clock The pixel clock LCD_PCLK frequency is derived from LCD_CLK the reference clock to this LCD module se...

Page 934: ...Vertical Clock LCD_VSYNC LCD_VSYNC toggles after all lines in a frame have been transmitted to the LCD and a programmable number of line clock cycles has elapsed both at the beginning and end of each frame The RASTER_TIMING_1 register fully defines the behavior of this signal LCD_VSYNC can be programmed to be synchronized with the rising or falling edge of LCD_PCLK The configuration field is bits ...

Page 935: ...assive mode the pixel clock transitions only when valid data is available on the data lines In active mode the pixel clock transitions continuously and the ac bias pin is used as an output enable to signal when data is available on the LCD pin LIDD character not used LIDD graphics 6800 mode enable strobe 8080 mode read strobe LCD_AC_ENB_CS OUT Raster controller ac bias used to signal the LCD to sw...

Page 936: ... buffer is used these two registers will not be used LCDDMA_FB1_CEILING In addition the LIDD_CTRL register for LIDD Controller or the RASTER_CTRL register for Raster Controller should also be configured appropriately along with all the timing registers To enable DMA transfers the LIDD_DMA_EN bit in the LIDD_CTRL register or the LCDEN bit in the RASTER_CTRL register should be written with 1 NOTE If...

Page 937: ...ounter reloads the value in field ACB_I but does not start to decrement until the ABC bit is cleared by writing 0 to this bit 5 Frame transfer completed When one frame of data is transferred completely the DONE bit in the LCD_STAT register is set This bit is cleared by disabling the Raster Controller i e clearing the LCDEN bit in the RASTER_CTRL register Note that the EOF0 and EOF1 bits in the LCD...

Page 938: ...cter Display HD44780 Type 8 100 LCD_D 7 0 DATA 7 0 Data Bus length defined by Instruction LCD_HSYNC R W Read Write LCD_VSYNC RS Register Select RS 0 command RS 1 data LCD_AC_ENB_CS E or E0 Enable Strobe first display LCD_MCLK E1 Enable Strobe second display optional Micro Interface Graphic Display 6800 Family Up to 16 001 LCD_D 15 0 DATA 15 0 Data Bus 16 bits always available LCD_PCLK E Enable Clo...

Page 939: ...gnals when this mode is active Table 23 4 Operation Modes Supported by Raster Controller Interface Data Bus Width Register Bits RASTER_CTRL 9 7 1 Signal Name Description Passive STN Mono 4 bit 4 001 LCD_D 3 0 Data bus LCD_PCLK Pixel clock LCD_HSYNC Horizontal clock Line Clock LCD_VSYNC Vertical clock Frame Clock LCD_AC_ENB_CS AC Bias LCD_MCLK Not used Passive STN Mono 8 bit 8 101 LCD_D 7 0 Data bu...

Page 940: ...passive STN versus active TFT various BPP size Figure 23 3 shows that The gray scaler serializer and output FIFO blocks are bypassed in active TFT modes The palette is bypassed in both 12 and 16 BPP modes Figure 23 3 Logical Data Path for Raster Controller In summary The display image is stored in frame buffers The built in DMA engine constantly transfers the data stored in the frame buffers to th...

Page 941: ...ytes are still considered a palette The first entry should be 4000h bit 14 is 1 while the remaining entries must be filled with 0 For details see Table 23 5 Each entry in a palette occupies 2 bytes As a result 8 BPP mode palette has 256 color entries while the other palettes have up to 16 color entries 4 BPP mode uses up the all the 16 entries in a palette 1 BPP mode uses the first 2 entries in a ...

Page 942: ...42 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC The equations shown in Table 23 6 are used to calculate the total frame buffer size in bytes based on varying pixel size encoding and screen sizes Figure 23 5 and Figure 23 6 show more detail of the palette entry organization Table 23...

Page 943: ... Base FEh Unused BPP A www ti com Architecture 943 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC Figure 23 6 256 Entry Palette Buffer Format 8 BPP Bits 12 13 and 14 of the first palette entry select the number of bits per pixel to be used in the following frame and thus the number o...

Page 944: ...13 14 12 bits pixel Bit Pixel 0 Pixel 1 Bit 15 0 Base 2 Unused Architecture www ti com 944 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC Figure 23 8 12 BPP Data Memory Organization Little Endian Unused 15 12 bits are filled with zeroes in TFT mode Figure 23 9 8 BPP Data Memory Organ...

Page 945: ... supported The PLM field in RASTER_CTRL affects the palette loading If PLM is 00b palette plus data mode or 01b palette only mode the palette is loaded by the DMA engine at the very beginning which is followed by the loading of pixel data If PLM is 10b data only mode the palette is not loaded Instead the DMA engine loads the pixel data immediately 23 2 5 4 Gray Scaler Serializer 23 2 5 4 1 Passive...

Page 946: ... Active Mode TFT_STN 1 Monochrome MONO_COLOR 1 Color MONO_COLOR 0 Color Only MONO_COLOR 0 1 2 palette entries to select within 15 grayscales 2 palette entries to select within 3375 possible colors 2 palette entries to select within 4096 possible colors 2 4 palette entries to select within 15 grayscales 4 palette entries to select within 3375 possible colors 4 palette entries to select within 4096 ...

Page 947: ...m Architecture 947 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC 23 2 5 5 Output Format 23 2 5 5 1 Passive STN Mode As shown in Figure 23 3 the pixel data stored in frame buffers go through palette if applicable and gray scaler serializer before reaching the Output FIFO As a result ...

Page 948: ...e first or last few lines of the LCD panel see Figure 23 14 This is mainly used for power saving This is supported by the Raster Controller via its subpanel feature The RASTER_SUBPANEL register fully defines its behavior that is the following parameters are defined Whether the first or last few lines will be refreshed A line number which is the last or first line to be refreshed The pixel data to ...

Page 949: ...rite Register Section 23 3 7 28h RASTER_CTRL LCD Raster Control Register Section 23 3 8 2Ch RASTER_TIMING_0 LCD Raster Timing 0 Register Section 23 3 9 30h RASTER_TIMING_1 LCD Raster Timing 1 Register Section 23 3 10 34h RASTER_TIMING_2 LCD Raster Timing 2 Register Section 23 3 11 38h RASTER_SUBPANEL LCD Raster Subpanel Display Register Section 23 3 12 40h LCDDMA_CTRL LCD DMA Control Register Sect...

Page 950: ...CD Controller in Raster mode The 8 bit clock divider CLKDIV field is used to select the frequency of the pixel clock CLKDIV can generate a range of pixel clock frequencies from LCD_CLK 2 to LCD_CLK 255 The pixel clock frequency must be adjusted to meet the required screen refresh rate The refresh rate depends on The number of pixels for the target display Whether monochrome or color mode is select...

Page 951: ...imitations shown in Table 23 12 If CLKDIV equals 0 or 1 the effect is undefined Dividing the pixel clock frequency by an odd number distorts the duty cycle Table 23 12 Pixel Clock Frequency Programming Limitations Type of Screen Output In Bits Minimum Pixel Clock Divider TFT 1 2 4 8 BPP 12 1 pixel 2 TFT 16 BPP 16 1 pixel 2 STN monochrome 4 output lines per panel 4 4 pixel 4 STN monochrome 8 output...

Page 952: ...iptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 EOF1 End of Frame 1 0 no end of frame 1 detected 1 end of frame 1 detected 8 EOF0 End of Frame 0 0 no end of frame 0 detected 1 end of frame 0 detected 7 Reserved 0 Reserved 6 PL Loaded Palette 0 The palette is not loaded 1 The palette is loaded 5 FUF FIFO Underflow Status 0 FIFO has not underrun 1 LCD dither logic not supplying data ...

Page 953: ...0h Increase priority for LCD controller DMA Increase burst size setting for LCD controller DMA Run the EMIFB if used at maximum clock speed This bit is cleared by disabling the LCD controller RASTER_EN 0 This also resets the input FIFO in the DMA controller SYNC 1 when a frame synchronization lost occurred SYNC 0 as long as no frame synchronization error occurs 23 3 3 3 AC Bias Count Status ABC Th...

Page 954: ...is a read only bit that is set after the LCD finished loading the palette into memory PL 1 when the palette is loaded PL 0 as long as the palette is not loaded In data only PL 10 and palette plus data PL 00 modes write 0 to clear the interrupt However in the palette only PL 01 mode LCD must be turned off in order to reset clear the interrupt But in this particular mode make sure not to turn off th...

Page 955: ...ved 0 Reserved 10 DONE_INT_EN LIDD Frame Done Interrupt Enable 0 Disable LIDD Frame Done interrupt 1 Enable LIDD Frame Done interrupt seen on LCD Status Reg bit 0 9 DMA_CS0_CS1 CS0 CS1 Select for LIDD DMA writes 0 DMA writes to LIDD CS0 1 DMA writes to LIDD CS1 8 LIDD_DMA_EN LIDD DMA Enable 0 Deactivate DMA control of LIDD interface DMA control is released upon completion of transfer of the curren...

Page 956: ...escription 3 RSPOL Register Select RS Polarity Control 0 Do Not Invert RS 1 Invert RS RS is active low by default 2 0 LIDD_MODE_SEL 0 7h LIDD Mode Select Selects type of LCD interface for the LIDD to drive LIDD_MODE_SEL defines the function of LCD external pins as follows Pin 001b 011b 100b LCD_PCLK E RD N A LCD_HSYNC R W WR R W LCD_VSYNC RS RS RS LCD_AC_ENB_CS CS0 CS0 E0 LCD_MCLK CS1 CS1 E1 0 Syn...

Page 957: ...d Output Enable ALE Direction bit and Chip Select 0 have been set up before the Write Strobe is asserted when performing a write access 26 21 W_STROBE 1 3Fh Write Strobe Duration cycles Field value defines number of MCLK cycles that the Write Strobe is held active when performing a write access 20 17 W_HOLD 1 Fh Write Strobe Hold cycles Field value defines number of MCLK cycles that the Data Bus P...

Page 958: ... ADR_INDX field of this register Similarly writing to LIDD_CS1_ADDR asserts CS1 and Address Latch Enable which loads the ADR_INDX field of this register into the address generator of the peripheral device Likewise reading from LIDD_CS1_ADDR asserts CS1 and Address Latch Enable which loads status information from the peripheral device into the ADR_INDX field of this register The LIDD_CSn_ADDR is sh...

Page 959: ...ral device into the DATA field of this register Similarly writing to LIDD_CS1_DATA asserts CS1 and deasserts Address Latch Enable which loads the DATA field of this register into the peripheral device Likewise reading from LIDD_CS1_DATA asserts CS1 and deasserts Address Latch Enable which loads data from the peripheral device into the DATA field of this register The LIDD_CSn_DATA is shown in Figur...

Page 960: ... bits of pixel data is processed and output i e X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 where X is ignored by the Raster Controller 1 Enabled Pixel data in the frame buffer is 16 bit but only 12 of the bits are processed and output i e R3 R2 R1 R0 X G3 G2 G1 G0 X X B3 B2 B1 B0 X where X is ignored by the Raster Controller The data patterns above refer to frame buffer bits not output bits 23 TF...

Page 961: ...word 7 TFT_STN TFT or STN Mode 0 Passive STN display operation enabled 1 Active TFT display operation enabled 6 FUF_EN FIFO Underflow Interrupt Enable 0 Disable the FIFO Underflow interrupt 1 Enable the FIFO Underflow interrupt 5 SL_EN Sync Lost Interrupt Enable 0 Disable the Sync Lost interrupt 1 Enable the Sync Lost interrupt 4 PL_EN Palette Loaded Interrupt Enable 0 Disable the Palette Loaded i...

Page 962: ...t request If the LCD controller is disabled the signals on pixel data 15 0 pins are set to 0 and the pixel clock frame clock vertical clock line clock horizontal clock and ac bias signals are set to their inactive state This can be 0 or 1 depending on the inversions programmed in the LCD Raster Timing 2 register 23 3 8 2 LCD Monochrome MONO_COLOR The color monochrome select LcdBW bit is used to de...

Page 963: ...isplay Controller LCDC 23 3 8 3 TFT_STN TFT_STN The TFT_STN TFT_STN bit selects whether the LCD controller operates in passive STN or active TFT display control mode When TFT_STN 0 passive or STN mode is selected LCD data flows from the frame buffer memory via the LCD dedicated DMA channel to the palette the palette is bypassed for the 12 and 16 BPP modes to the dithering logic and the output FIFO...

Page 964: ...c only supports 4 bits to encode each color component R G B that limits the pixel encoding size in passive mode Increasing the size of the pixel representation allows a total of 64K colors to be addressed using an off chip palette in conjunction with the LCD controller 23 3 8 4 Mono 8 Bit Mode MONO8B NOTE MONO8B does not affect any of the color modes or TFT The mono 8 bit mode MONO8B bit selects w...

Page 965: ... the palette was previously loaded There is no need to keep loading the palette if it is not changing As a matter of fact in data only mode the BPP is fixed and can not change on the fly since the palette is not loaded at every frame PLM 3h is reserved 23 3 8 7 TFT Alternate Signal Mapping TFT_ALT_MAP This bit is relevant only if TFT_ALT_MAP 1 This bit field controls how the TFT pixel data is outp...

Page 966: ...s as shown in Figure 23 27 Figure 23 27 12 Bit STN Data in Frame Buffer Pins 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Data Ignored R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 If STN_565 1 the 16 bit STN mode is selected The only difference from the 12 BPP mode is how the pixel data is organized in the frame buffer and which bits are sent to the dither logic The 16 bit STN mode appears in frame buffer me...

Page 967: ... 0 FFh Horizontal Front Porch Encoded value HFP 1 is used to specify number of LCD_PCLKs to add to the end of a line transmission before line clock is asserted program to value minus one Note that pixel clock is held in its inactive state during the end of line wait period in STN mode while it is active in TFT mode 15 10 HSW 0 3Fh Horizontal Sync Pulse Width Encoded value HSW 1 is used to specify ...

Page 968: ...rch HFP NOTE The pixel clock does not transition during these dummy pixel clock cycles in passive display mode but it transitions continuously in active display mode The 8 bit horizontal front porch HFP field is used to specify the number of dummy pixel clocks to insert at the end of each line or row of pixels before pulsing the line clock or LCD_HSYNC pin Once a complete line of pixels is transmi...

Page 969: ...ing the insertion of the extra line clock periods 23 16 VFP 0 FFh Vertical Front Porch Encoded value VFP used to specify number of line clock LCD_HSYNC periods to add to the end of each frame Note that the line clock transitions during the insertion of the extra line clock periods 15 10 VSW 0 3Fh Vertical Synchronization Pulse Width In TFT mode encoded value VSW 1 defines the number of line clock ...

Page 970: ...lse width ranging from 1 64 line clock periods program to value required minus 1 see Figure 23 32 The following frame starts after LCD_VSYNC is deasserted and a programmable number of line clock delays VBP has elapsed Figure 23 32 Vertical Synchronization Pulse Width VSW Active Mode 23 3 10 2 2 Passive Mode NOTE The pixel clock does not transition during the whole dummy line clock periods that are...

Page 971: ...mber that VSW must be programmed to value required minus 1 The 8 bit vertical front porch VFP field is used to specify the number of line clocks to insert at the end of each frame Once a complete frame of pixels is transmitted to the LCD display the value in VFP is used to count the number of line clock periods to wait After the count has elapsed the LCD_VSYNC signal is pulsed in active mode or ex...

Page 972: ...te to be completely filled via the DMA and allows a sufficient number of encoded pixel values to be input from the frame buffer processed by the dither logic then placed in the output FIFO ready to be output to the LCD data lines The 8 bit vertical back porch VBP field is used to specify the number of line clocks or LCD_HSYNC to insert at the beginning of each frame The VBP count starts just after...

Page 973: ...to activate and deactivate LCD_HSYNC and LCD_VSYNC 24 SYNC_EDGE Horizontal and Vertical Sync Edge The activation and deactivation of LCD_HSYNC and LCD_VSYNC will occur on the defined LCD_PCLK edge 0 Rising edge 1 Falling edge SYNC_CTRL must be active in order to use this bit 23 BIAS Invert AC Bias 0 LCD_AC_ENB_CS is an active high pulse 1 LCD_AC_ENB_CS is an active low pulse In STN mode the activa...

Page 974: ...d minus 1 This line is used by the LCD display to periodically reverse the polarity of the power supplied to the screen to eliminate DC offset 23 3 11 2 AC Bias Line Transitions Per Interrupt ACB_I The 4 bit ac bias line transitions per interrupt ACB_I field is used to specify the number of line transitions to count before setting the ac bias count status ABC bit in the LCD controller status regis...

Page 975: ...0 the ac bias pin is active high 23 3 11 7 Horizontal and Vertical Sync Edge SYNC_EDGE This bit determines whether the HSYNC VSYNC is driven on the rising or falling edge of the pixel clock see the SYNC_CTRL bit SYNC_CTRL must be turned on first By default the LCD_HSYNC and LCD_VSYNC signals are driven on the falling edge of the pixel clock and the pixel data is driven on the rising edge of pixel ...

Page 976: ...k SYNC_CTRL 1 LCD_HSYNC and LCD_VSYNC signals are driven according to the SYNC_EDGE bit SYNC_EDGE 0 LCD_HSYNC and LCD_VSYNC signals are driven on the falling edge of the pixel clock Figure 23 37 SYNC_CTRL 1 SYNC_EDGE 0 and IPC 1 23 3 11 8 Horizontal and Vertical Sync Control SYNC_CTRL This bit enables disables the possibility to make HSYNC and VSYNC programmable When SYNC_CTRL 1 HSYNC and VSYNC ar...

Page 977: ...R Read only n value after reset Table 23 23 LCD Raster Subpanel Display Register RASTER_SUBPANEL Field Descriptions Bit Field Value Description 31 SPEN Subpanel Enable 0 Disabled 1 Enabled 30 Reserved 0 Reserved 29 HOLS High or Low Signal The field indicates the position of subpanel compared to the LPPT value 0 Low below 1 High above 28 26 Reserved 0 Reserved 25 16 LPPT 0 3FFh Line Per Panel Thres...

Page 978: ...begins to be displayed The rest of the screen is filled with DPD value Figure 23 39 Subpanel Display SPEN 1 HOLS 1 When HOLS 0 the beginning of the screen is filled with DPD value until the LPPT excluded From the LPPT line number the rest of the screen below LPPT displays the image from system memory Figure 23 40 Subpanel Display SPEN 1 HOLS 0 The bottom of the panel is line 0 and top line of the ...

Page 979: ...1 11 Reserved 0 Reserved 10 7 Reserved 0 Reserved 6 4 BURST_SIZE 0 7h Burst Size setting for DMA transfers all DMA transfers are 32 bits wide 0 Burst size of 1 1h Burst size of 2 2h Burst size of 4 3h Burst size of 8 4h Burst size of 16 5h 7h Reserved 3 Reserved 0 Reserved 2 EOF_INTEN End of Frame Interrupt Enable Setting this bit allows the end of frame 0 or 1 status bits in the LCD status regist...

Page 980: ...dress Register LCDDMA_FBn_BASE Field Descriptions Bit Field Value Description 31 0 FBn_BASE 0 FFFF FFFFh Frame Buffer n Base Address pointer Note The 2 LSBs are hardwired to 00b 23 3 15 LCD DMA Frame Buffer n Ceiling Address Registers LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING The LCD DMA frame buffer n ceiling address register LCDDMA_FBn_CEILING contains the ending address for frame buffer n speci...

Page 981: ...rated Multichannel Audio Serial Port McASP Chapter 24 SPRUH91D March 2013 Revised September 2016 Multichannel Audio Serial Port McASP This chapter describes the multichannel audio serial port McASP See your device specific data manual to determine how many McASPs are available on your device Topic Page 24 1 Registers 1036 ...

Page 982: ...c generator TDM streams from 2 to 32 and 384 time slots Support for time slot sizes of 8 12 16 20 24 28 and 32 bits Data formatter for bit manipulation Up to 16 individually assignable serial data pins McASP0 can have up to 16 serial data pins McASP1 can have up to 12 serial data pins McASP2 can have up to 4 serial data pins Glueless connection to audio analog to digital converters ADC digital to ...

Page 983: ... frame sync polarity rising or falling edge ACLKR X AHCLKR X and AFSR X Slot length number of bits per time slot 8 12 16 20 24 28 32 bits supported Word length bits per word 8 12 16 20 24 28 32 bits always less than or equal to the time slot length First bit data delay 0 1 2 bit clocks Left right alignment of word inside slot Bit order MSB first or LSB first Bit mask pad rotate function Automatica...

Page 984: ...O FIFO CONTROL STATUS AXEVT AREVT DMA events DMA bus Peripheral configuration bus Pin function control www ti com 984 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP 24 0 18 Functional Block Diagram A block diagram of the McASP is shown in Figure 24 1 The McASP has independent receive t...

Page 985: ... Amp Stereo I2S www ti com 985 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP 24 0 18 1 System Level Connections Figure 24 2 through Figure 24 5 show examples of McASP usage in digital audio encoder decoder systems Figure 24 2 McASP to Parallel 2 Channel DACs Figure 24 3 McASP to 6 Cha...

Page 986: ... generator Stereo I2S Digital amp Digital amp Digital Digital amp amp generator PWM generator generator PWM PWM www ti com 986 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP Figure 24 4 McASP to Digital Amplifier Figure 24 5 McASP as Digital Audio Encoder ...

Page 987: ...rial transfer the clock the data and the frame sync In a TDM transfer all data bits AXR n are synchronous to the serial clock ACLKX or ACLKR The data bits are grouped into words and slots as defined in Section 24 0 19 The slots are also commonly referred to as time slots or channels in TDM terminology A frame consists of multiple slots or channels Each TDM frame is defined by the frame sync signal...

Page 988: ...l DAC may be designed to transfer over a single serial data pin AXR n as shown in Figure 24 6 In this case the serial clock must run fast enough to transfer a total of 6 channels within each frame period Alternatively a similar six channel DAC may be designed to use three serial data pins AXR 0 1 2 transferring two channels of data on each pin during each sample period Figure 24 8 In the latter ca...

Page 989: ... two logical states form a cell The duration of the cell which equals to the duration of the data bit is called a time interval A logical 1 is represented by two transitions of the signal within a time interval which corresponds to a cell with logical states 01 or 10 A logical 0 is represented by one transition within a time interval which corresponds to a cell with logical states 00 or 11 In addi...

Page 990: ... may carry any other information Time interval 28 carries the validity bit V associated with the main data field in the subframe Time interval 29 carries the user data channel U associated with the main data field in the subframe Time interval 30 carries the channel status information C associated with the main data field in the subframe The channel status indicates if the data in the subframe is ...

Page 991: ...annel operation mode the samples taken from both channels are transmitted by time multiplexing in consecutive subframes Both subframes contain valid data The first subframe left or A channel in stereophonic operation and primary channel in monophonic operation normally starts with preamble M However the preamble of the first subframe changes to preamble B once every 192 frames to identify the star...

Page 992: ... is marked by an edge of the serial clock The duration of a bit is a serial clock period A 1 is represented by a logic high on the AXR n pin for the entire duration of the bit A 0 is represented by a logic low on the AXR n pin for the entire duration of the bit Word A word is a group of bits that make up the data being transferred between the DSP and the external device Figure 24 12 shows an 8 bit...

Page 993: ...zeros 87h as 8 bit word 12 bit slot b right align MSB first pad zeros left align LSB first pad zeros 87h as 8 bit word 12 bit slot c right align LSB first pad zeros 87h as 8 bit word 12 bit slot d 87h as 8 bit word 12 bit slot left align MSB first pad with bit 7 e 87h as 8 bit word 12 bit slot right align MSB first pad with bit 4 f 87h as 8 bit word 12 bit slot left align LSB first pad with bit 7 ...

Page 994: ...nition of the frame sync See Section 24 0 18 1 Section 24 0 18 2 and Section 24 0 21 2 1 for details on the frame sync formats required for the different transfer modes and protocols burst mode TDM mode and I2S format DIT mode and S PDIF format Figure 24 14 Definition of Frame and Frame Sync Width 1 In this example there are two slots in a frame and FS duration of slot length is shown Other terms ...

Page 995: ... out AMUTEIN McASP mute input from external device AMUTE McASP mute output Data pins AXR n 24 0 21 Clock and Frame Sync Generators The McASP clock generators are able to produce two independent clock zones transmit and receive clock zones The serial clock generators may be programmed independently for the transmit section and the receive section and may be completely asynchronous to each other The...

Page 996: ...the rising edge of the internal transmit clock XCLK Figure 24 15 The CLKXP mux determines if ACLKX needs to be inverted to become XCLK If CLKXP 0 the CLKXP mux directly passes ACLKX to XCLK As a result the McASP shifts transmit data at the rising edge of ACLKX If CLKXP 1 the CLKX mux passes the inverted version of ACLKX to XCLK As a result the McASP shifts transmit data at the falling edge of ACLK...

Page 997: ...ternally generated or externally sourced polarity of the clock may be programmed CLKRP to be either rising or falling edge The receive high frequency master clock AHCLKR may be either externally sourced from the AHCLKR pin or internally generated as selected by the HCLKRM bit If internally generated HCLKRM 1 the clock is divided down by a programmable divider HCLKRDIV from AUXCLK The receive high ...

Page 998: ...or is shown in Figure 24 17 The frame sync options are programmed by the receive and transmit frame sync control registers AFSRCTL and AFSXCTL The options are Internally generated or externally generated Frame sync polarity rising edge or falling edge Frame sync width single bit or single word Bit delay 0 1 or 2 cycles before the first data bit The transmit frame sync pin is AFSX and the receive f...

Page 999: ...ifts out data to the serial data pin AXR n When configured as a receiver the serializer shifts in data from the AXR n pin The serializer is clocked from the transmit receive section clock ACLKX ACLKR if configured to transmit receive respectively All serializers that are configured to transmit operate in lock step Similarly all serializers that are configured to receive also operate in lock step T...

Page 1000: ...s or perform sign extension Since all transmitters share the same data formatting unit the McASP only supports one transmit format at a time For example the McASP will not transmit in I2S format on serializer 0 while transmitting Left Justified on serializer 1 Likewise the receiver section of the McASP only supports one data format at a time and this format applies to all receiving serializers How...

Page 1001: ...ve in an LSB first order Finally note that the R X DATDLY bits in R X FMT also determine the data format For example the difference between I2S format and left justified is determined by the delay between the frame sync edge and the first data bit of a given time slot For I2S format R X DATDLY should be set to a 1 bit delay whereas for left justified format it should be set to a 0 bit delay The co...

Page 1002: ...recover from transmit and receive clock failures See Section 24 0 21 6 6 for implementation and programming details 24 0 21 6 Pin Function Control All McASP pins except AMUTEIN are bidirectional input output pins In addition these bidirectional pins function either as McASP or general purpose I O GPIO pins The following registers control the pin functions Pin function register PFUNC selects pin to...

Page 1003: ...parate control of pin direction by PDIR and the choice of internal versus external clocking by CLKRM CLKXM Depending on the specific device and usage you might select an external clock CLKRM 0 while enabling the internal clock divider and the clock pin as an output in the PDIR register PDIR ACLKR 1 In this case the bit clock is an output PDIR ACLKR 1 and therefore routed to the ACLKR pin However b...

Page 1004: ...eral Purpose Output Pin Initialization Using PDOUT All pins default as inputs To initialize a pin as output you should follow this sequence 1 PDIR n 0 default as input 2 PFUNC n 1 GPIO function 3 PDOUT n desired output value 4 PDIR n 1 change to output after desired value is configured in PDOUT n Example 24 3 General Purpose Output Pin Change Data from 0 to 1 Using PDSET If the pin is already conf...

Page 1005: ...lization This section discusses steps necessary to use the McASP module 24 0 21 1 1 Considerations When Using a McASP The following is a list of things to be considered for systems using a McASP 24 0 21 1 1 1 Clocks For each receive and transmit section External or internal generated bit clock and high frequency clock If internally generated what is the bit clock speed and the high frequency clock...

Page 1006: ...FMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RCLKCHK If external clocks AHCLKR and or ACLKR are used they must be running already for proper synchronization of the GBLCTL register b Transmit registers XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XCLKCHK If external clocks AHCLKX and or ACLKX are used they must be running already for proper synchronization of the GBLCTL register c Serializer r...

Page 1007: ...4 second waveform As soon as the transmit serializer is taken out of reset XDATA in the XSTAT register is set indicating that XBUF is empty and ready to be serviced The XDATA status causes a DMA event AXEVT to be generated and can cause an interrupt AXINT to be generated if it is enabled in the XINTCTL register a If DMA is used to service the McASP the DMA automatically services the McASP upon rec...

Page 1008: ...ns Also make sure that the initialization or reinitialization sequence follows the guidelines in Bits With Restrictions on When They May be Changed 24 0 21 1 4 Importance of Reading Back GBLCTL In Section 24 0 21 1 2 steps 4b 5b 7c 9b and 10b state that GBLCTL should be read back until the bits that were written are successfully latched This is important because the transmitter and receiver state ...

Page 1009: ...hronously 24 0 21 2 Transfer Modes 24 0 21 2 1 Burst Transfer Mode The McASP supports a burst transfer mode which is useful for nonaudio data such as passing control information between two DSPs Burst transfer mode uses a synchronous serial format similar to the TDM mode The frame sync generation is not periodic or time driven as in TDM mode but data driven and the frame sync is generated for each...

Page 1010: ...eft at default 0 to select non DIT mode Leave the register at default RMASK XMASK Mask desired bits according to Section 24 0 21 2 and Section 24 0 21 4 RFMT XFMT Program all fields according to data format desired See Section 24 0 21 4 AFSRCTL AFSXCTL Clear RMOD XMOD bits to 0 to indicate burst mode Clear FRWID FXWID bits to 0 for single bit frame sync duration Configure other fields as desired A...

Page 1011: ...desired PDOUT PDIN PDSET PDCLR Not applicable Leave at default GBLCTL Follow the initialization sequence in Section 24 0 21 1 2 to configure this register AMUTE Program all fields according to mute control desired DLBCTL If loopback mode is desired configure this register according to Section 24 0 21 7 otherwise leave this register at default DITCTL DITEN must be left at default 0 to select TDM mo...

Page 1012: ...me slot M 1 In this case slot M is the next active time slot The DMA event for time slot M is generated during the first bit time of slot M 1 The receive DMA request generation does not need this capability since the receive DMA event is generated after data is received in the buffer looks back in time If a time slot is disabled then no data is copied to the buffer for that time slot and no DMA ev...

Page 1013: ...at the TDM slot counter counts the DIT subframes To transmit data in the DIT mode the following pins are typically needed AHCLKX transmit high frequency master clock One or more serial data pins AXR n whose serializers have been configured to transmit AHCLKX is optional the internal clock source may be used instead but if used as a reference the DSP provides a clock check circuit that continually ...

Page 1014: ...ter AMUTE Program all fields according to mute control desired DLBCTL Not applicable Loopback is not supported for DIT mode Leave at default DITCTL DITEN bit must be set to 1 to enable DIT mode Configure other bits as desired RMASK Not applicable Leave at default RFMT Not applicable Leave at default AFSRCTL Not applicable Leave at default ACLKRCTL Not applicable Leave at default AHCLKRCTL Not appl...

Page 1015: ...RA5 The 192 bits in these six registers contain the user data information for the LEFT channel within each frame DITUDRB0 to DITUDRB5 The 192 bits in these six registers contain the user data information for the RIGHT channel within each frame The S PDIF block format is shown in Figure 24 11 There are 192 frames within a block frame 0 to frame 191 Within each frame there are two subframes subframe...

Page 1016: ...UDRB1 32 1 L M DITCSRA1 0 DITUDRA1 0 32 2 R W DITCSRB1 0 DITUDRB1 0 63 1 L M DITCSRA1 31 DITUDRA1 31 63 2 R W DITCSRB1 31 DITUDRB1 31 Defined by DITCSRA2 DITCSRB2 DITUDRA2 DITUDRB2 64 1 L M DITCSRA2 0 DITUDRA2 0 64 2 R W DITCSRB2 0 DITUDRB2 0 95 1 L M DITCSRA2 31 DITUDRA2 31 95 2 R W DITCSRB2 31 DITUDRB2 31 Defined by DITCSRA3 DITCSRB3 DITUDRA3 DITUDRB3 96 1 L M DITCSRA3 0 DITUDRA3 0 96 2 R W DITC...

Page 1017: ...rrupt AXINT is also generated if XDATA interrupt is enabled in the XINTCTL register See Section 24 0 21 5 1 for details For DMA requests the McASP does not require XSTAT to be read between DMA events This means that even if XSTAT already has the XDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep only one DMA event is gen...

Page 1018: ...F ready status An interrupt ARINT is also generated if RDATA interrupt is enabled in the RINTCTL register See Section 24 0 21 5 2 for details For DMA requests the McASP does not require RSTAT to be read between DMA events This means that even if RSTAT already has the RDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep onl...

Page 1019: ...tive receivers the DMA CPU should read from the RBUF DMA port address four times to obtain data for serializers 1 2 3 and 6 in this exact order upon each receive data ready event When transmitting the DMA CPU must write data to each serializer configured as active and transmit within each time slot Failure to do so results in a buffer underrun condition Section 24 0 21 6 2 Similarly when receiving...

Page 1020: ...rough the DMA port or through the peripheral configuration port To use the CPU to service the McASP through interrupts the XSTAT RSTAT bit must be enabled in the respective XINTCTL RINTCTL registers to generate interrupts AXINT ARINT to the CPU upon data ready 24 0 21 3 5 Using the DMA for McASP Servicing The most typical scenario is to use the DMA to service the McASP through the DMA port althoug...

Page 1021: ...ASP Audio FIFO AFIFO Block Diagram AFIFO Data Transmission When the Write FIFO is disabled transmit DMA requests pass through directly from the McASP to the host DMA controller Whether the WFIFO is enabled or disabled the McASP generates transmit DMA requests as needed the AFIFO is invisible to the McASP When the Write FIFO is enabled transmit DMA requests from the McASP are sent to the AFIFO whic...

Page 1022: ...s until this condition has been satisfied at that point it reads RNUMDMA words from the McASP See description for RFIFOCTL RNUMDMA in Section 24 1 47 If the host CPU reads the Read FIFO independent of a receive DMA request and the RFIFO at that time contains less than RNUMEVT words those words will be read correctly emptying the FIFO Receive DMA Event Pacer The AFIFO may be configured to delay mak...

Page 1023: ...word size WORD in Table 24 4 options are multiples of 4 since the transmit rotate right unit only supports rotation by multiples of 4 However the bit mask pad unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is ...

Page 1024: ...1 M L P P XROT WORD m Out MSB first LEFT aligned M M 1 L P P XRVRS 1 reverse P P L M 1 M DSP REP Integer P L M P M 1 Data flow P P P P M M 1 L XROT SLOT P P n Out MSB first RIGHT aligned XRVRS 1 reverse P P M M 1 L P P L M 1 M DSP REP Integer P L P M M 1 Data flow XROT 0 P L M P M 1 XRVRS 0 no reverse P L P M M 1 o Out LSB first LEFT aligned L M 1 M P P DSP REP Integer P L M P M 1 Data flow P P P ...

Page 1025: ...ions are multiples of 4 since the receive rotate right unit only supports rotation by multiples of 4 However the bit mask pad unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is possible to set the bit mask unit...

Page 1026: ...2 DSP REP Q31 M L M 1 P P RROT 0 M M 1 L P P M M 1 L P P RRVRS 0 no reverse RROT 0 M 1 P P M L RRVRS 1 reverse f In MSB first RIGHT aligned P P M M 1 L L M 1 M P P Data flow Data flow Data flow Data flow Data flow M 1 P P M L Data flow M 1 P P M RROT 32 SLOT L L M 1 M P P g In LSB first LEFT aligned RRVRS 0 no reverse M 1 P P M P P L RROT 32 WORD M 1 M 1 DSP REP Integer P P M P P M L L Data flow P...

Page 1027: ... Interrupts Upon detection the following error conditions generate interrupt flags In the receive status register RSTAT Receiver overrun ROVRN Unexpected receive frame sync RSYNCERR Receive clock failure RCKFAIL Receive DMA error RDMAERR In the transmit status register XSTAT Transmit underrun XUNDRN Unexpected transmit frame sync XSYNCERR Transmit clock failure XCKFAIL Transmit DMA error XDMAERR E...

Page 1028: ...h GPIO so GPIO function must be set to McASP for automatic mute function www ti com 1028 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP When one or more of the errors is detected and enabled the AMUTE device pin is driven to an active state that is selected by MUTEN in AMUTE The active...

Page 1029: ...bust audio system the McASP includes error checking capability for the serial protocol data underrun and data overrun In addition the McASP includes a timer that continually measures the high frequency master clock every 32 AHCLKX AHCLKR clock cycles The timer value can be read to get a measurement of the clock frequency and has a minimum and maximum range setting that can set an error flag if the...

Page 1030: ...et the McASP and start again with the proper initialization In TDM mode during an underrun case a long stream of zeros are shifted out causing the DACs to mute To recover reset the McASP and start again with the proper initialization 24 0 21 6 3 Buffer Overrun Error Receiver A buffer overrun can only occur for serializers programmed to be receivers A buffer overrun occurs when the serializer is in...

Page 1031: ...clock failure check a Configure transmit clock failure detect logic XMIN XMAX XPS in the transmit clock check control register XCLKCHK b Clear transmit clock failure flag XCKFAIL in the transmit status register XSTAT c Wait until first measurement is taken 32 AHCLKX clock periods d Verify no clock failure is detected e Repeat steps b d until clock is running and is no longer issuing clock failure ...

Page 1032: ...n an out of range condition occurs An out of range minimum condition occurs when the count is smaller than XMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary XMAX This is in case the external clock completely stops so that the counter value is not copied to XCNT An out of range maximum condition occurs when the count i...

Page 1033: ... minimum allowable boundary RMIN and automatically flags an interrupt RCKFAIL in RSTAT when an out of range condition occurs An out of range minimum condition occurs when the count is smaller than RMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary RMAX This is in case the external clock completely stops so that the cou...

Page 1034: ...pback mode applies to TDM mode only 2 to 32 slots in a frame It does not apply to DIT mode XMOD 180h or burst mode XMOD 0 Figure 24 34 shows the basic logical connection of the serializers in loopback mode Two types of loopback connections are possible selected by the ORD bit in the digital loopback control register DLBCTL as follows ORD 0 Outputs of odd serializers are connected to inputs of even...

Page 1035: ...er GBLCTL Note that a valid serial clock must be supplied to the desired portion of the McASP transmit and or receive in order to assert the software reset bits in GBLCTL See Section 24 0 21 1 2 for details on how to ensure reset has occurred The entire McASP module may also be reset through the Power and Sleep Controller PSC Note that from the McASP perspective this reset appears as a hardware re...

Page 1036: ...ction 24 1 11 50h DITCTL DIT mode control register Section 24 1 12 60h RGBLCTL Receiver global control register Alias of GBLCTL only receive bits are affected allows receiver to be reset independently from transmitter Section 24 1 13 64h RMASK Receive format unit bit mask register Section 24 1 14 68h RFMT Receive bit stream format register Section 24 1 15 6Ch AFSRCTL Receive frame sync control reg...

Page 1037: ...hannel user data register DIT mode 2 Section 24 1 40 13Ch DITUDRA3 Left even TDM time slot channel user data register DIT mode 3 Section 24 1 40 140h DITUDRA4 Left even TDM time slot channel user data register DIT mode 4 Section 24 1 40 144h DITUDRA5 Left even TDM time slot channel user data register DIT mode 5 Section 24 1 40 148h DITUDRB0 Right odd TDM time slot channel user data register DIT mo...

Page 1038: ...ster for serializer 10 Section 24 1 42 22Ch XBUF11 1 Transmit buffer register for serializer 11 Section 24 1 42 230h XBUF12 1 Transmit buffer register for serializer 12 Section 24 1 42 234h XBUF13 1 Transmit buffer register for serializer 13 Section 24 1 42 238h XBUF14 1 Transmit buffer register for serializer 14 Section 24 1 42 23Ch XBUF15 1 Transmit buffer register for serializer 15 Section 24 1...

Page 1039: ...IFO Table 24 9 McASP AFIFO Registers Accessed Through Peripheral Configuration Port 1 Offset Acronym Register Description Section 1000h AFIFOREV AFIFO revision identification register Section 24 1 44 1010h WFIFOCTL Write FIFO control register Section 24 1 45 1014h WFIFOSTS Write FIFO status register Section 24 1 46 1018h RFIFOCTL Read FIFO control register Section 24 1 47 101Ch RFIFOSTS Read FIFO ...

Page 1040: ...XP x x x x x AHCLKXCTL HCLKXM x x x x x AHCLKRCTL HCLKRDIV x x x x x AHCLKRCTL HCLKRP x x x x x AHCLKRCTL HCLKRM x x x x x DLBCTL DLBEN x x x x x x DLBCTL ORD x x x x x x DLBCTL MODE x x x x x x 24 1 2 Revision Identification Register REV The revision identification register REV contains revision data for the peripheral The REV is shown in Figure 24 35 and described in Table 24 10 Figure 24 35 Rev...

Page 1041: ...a value other than 0 to reserved bits in this register may cause improper device operation This includes bits that are not implemented on a particular DSP Figure 24 36 Pin Function Register PFUNC 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 16 Reserved A R 0 15 14 13 12 11 10 9 8 AXR15 AXR14 AXR13 AXR12 AXR11 AXR10 AX...

Page 1042: ... GPIO pin 28 AFSX Determines if AFSX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 27 AHCLKX Determines if AHCLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 26 ACLKX Determines if ACLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 25 AMUTE Determines if AMUTE pin functi...

Page 1043: ... be set to 1 an output When AXR n is configured to transmit the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be set to 1 an output Similarly when AXR n is configured to receive the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be cleared to 0 an input CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cau...

Page 1044: ... as output 28 AFSX Determines if AFSX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 27 AHCLKX Determines if AHCLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 26 ACLKX Determines if ACLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 25 AMUTE Determines if AMUTE pin function...

Page 1045: ...writing a 0 has no effect and keeps the bits in PDOUT unchanged PDCLR when written to at this address writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0 writing a 0 has no effect and keeps the bits in PDOUT unchanged There is only one set of data out bits PDOUT 31 0 The other registers PDSET and PDCLR are just different addresses for the same control bits with different behav...

Page 1046: ...mines drive on AFSX output pin when the corresponding PFUNC 28 and PDIR 28 bits are set to 1 0 Pin drives low 1 Pin drives high 27 AHCLKX Determines drive on AHCLKX output pin when the corresponding PFUNC 27 and PDIR 27 bits are set to 1 0 Pin drives low 1 Pin drives high 26 ACLKX Determines drive on ACLKX output pin when the corresponding PFUNC 26 and PDIR 26 bits are set to 1 0 Pin drives low 1 ...

Page 1047: ... Table 24 14 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation This includes bits that are not implemented on a particular DSP Figure 24 39 Pin Data Input Register PDIN 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 16 Reserved A R 0 15 14...

Page 1048: ...el on ACLKR pin 0 Pin is logic low 1 Pin is logic high 28 AFSX Logic level on AFSX pin 0 Pin is logic low 1 Pin is logic high 27 AHCLKX Logic level on AHCLKX pin 0 Pin is logic low 1 Pin is logic high 26 ACLKX Logic level on ACLKX pin 0 Pin is logic low 1 Pin is logic high 25 AMUTE Logic level on AMUTE pin 0 Pin is logic low 1 Pin is logic high 24 16 Reserved 0 Reserved The reserved bit location a...

Page 1049: ...led by the same McASP The PDSET is shown in Figure 24 40 and described in Table 24 15 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation This includes bits that are not implemented on a particular DSP Figure 24 40 Pin Data Set Register PDSET 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A ...

Page 1050: ...to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 28 bit is set to 1 27 AHCLKX Allows the corresponding AHCLKX bit in PDOUT to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is set to 1 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be set to a logic high without affect...

Page 1051: ...olled by the same McASP The PDCLR is shown in Figure 24 41 and described in Table 24 16 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation This includes bits that are not implemented on a particular DSP Figure 24 41 Pin Data Clear Register PDCLR 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserve...

Page 1052: ...cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 28 bit is cleared to 0 27 AHCLKX Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is cleared to 0 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low wit...

Page 1053: ...effect If writing to this field always write the default value for future device compatibility 12 XFRST Transmit frame sync generator reset enable bit 0 Transmit frame sync generator is reset 1 Transmit frame sync generator is active When released from reset the transmit frame sync generator begins counting serial clocks and generating frame sync as programmed 11 XSMRST Transmit state machine rese...

Page 1054: ...e sync generator is active When released from reset the receive frame sync generator begins counting serial clocks and generating frame sync as programmed 3 RSMRST Receive state machine reset enable bit 0 Receive state machine is held in reset 1 Receive state machine is released from reset When released from reset the receive state machine immediately begins detecting frame sync and is ready to re...

Page 1055: ...DMA error RDMAERR drive AMUTE active enable bit 0 Drive is disabled Detection of receive DMA error is ignored by AMUTE 1 Drive is enabled active Upon detection of receive DMA error AMUTE is active and is driven according to MUTEN bit 10 XCKFAIL If transmit clock failure XCKFAIL drive AMUTE active enable bit 0 Drive is disabled Detection of transmit clock failure is ignored by AMUTE 1 Drive is enab...

Page 1056: ... MUTEN bit 4 INSTAT Determines drive on AXR n pin when PFUNC n and PDIR n bits are set to 1 0 AMUTEIN pin is inactive 1 AMUTEIN pin is active Audio mute in error is detected 3 INEN Drive AMUTE active when AMUTEIN error is active INSTAT 1 0 Drive is disabled AMUTEIN is ignored by AMUTE 1 Drive is enabled active INSTAT 1 drives AMUTE active 2 INPOL Audio mute in AMUTEIN polarity select bit 0 Polarit...

Page 1057: ... The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 3 2 MODE 0 3h Loopback generator mode bits Applies only when loopback mode is enabled DLBEN 1 0 Default and reserved on loopback mode DLBEN 1 When in non loopback mode DLBEN 0 MODE should be left at default 0...

Page 1058: ...tion always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 3 VB Valid bit for odd time slots DIT right subframe 0 V bit is 0 during odd DIT subframes 1 V bit is 1 during odd DIT subframes 2 VA Valid bit for even time slots DIT left subframe 0 V bit is 0 during even DIT subframes 1 V bit i...

Page 1059: ...ST x Transmit state machine reset enable bit A read of this bit returns the XSMRST bit value of GBLCTL Writes have no effect 10 XSRCLR x Transmit serializer clear enable bit A read of this bit returns the XSRCLR bit value of GBLCTL Writes have no effect 9 XHCLKRST x Transmit high frequency clock divider reset enable bit A read of this bit returns the XHCLKRST bit value of GBLCTL Writes have no eff...

Page 1060: ... W 0 23 22 21 20 19 18 17 16 RMASK23 RMASK22 RMASK21 RMASK20 RMASK19 RMASK18 RMASK17 RMASK16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 RMASK15 RMASK14 RMASK13 RMASK12 RMASK11 RMASK10 RMASK9 RMASK8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 RMASK7 RMASK6 RMASK5 RMASK4 RMASK3 RMASK2 RMASK1 RMASK0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND ...

Page 1061: ...riting to this field always write the default value for future device compatibility 17 16 RDATDLY 0 3h Receive bit delay 0 0 bit delay The first receive data bit AXR n occurs in same ACLKR cycle as the receive frame sync AFSR 1h 1 bit delay The first receive data bit AXR n occurs one ACLKR cycle after the receive frame sync AFSR 2h 2 bit delay The first receive data bit AXR n occurs two ACLKR cycl...

Page 1062: ...Slot size is 32 bits 3 RBUSEL Selects whether reads from serializer buffer XRBUF n by way of RBUFn by the CPU EDMA occur through the peripheral configuration port or the DMA port 0 Reads from XRBUF n originate on the DMA port Reads from XRBUF n on the peripheral configuration port are ignored 1 Reads from XRBUF n originate on the peripheral configuration port Reads from XRBUF n on the DMA port are...

Page 1063: ...ue for future device compatibility 15 7 RMOD 0 1FFh Receive frame sync mode select bits 0 Burst mode 1h Reserved 2h 20h 2 slot TDM I2S mode to 32 slot TDM 21h 17Fh Reserved 180h 384 slot TDM external DIR IC inputting 384 slot DIR frames to McASP over I2S interface 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has...

Page 1064: ... that this bitfield does not have any effect if ACLKXCTL ASYNC 0 see Section 24 1 29 for a description for the ASYNC bit 0 Falling edge Receiver samples data on the falling edge of the serial clock so the external transmitter driving this receiver must shift data out on the rising edge of the serial clock 1 Rising edge Receiver samples data on the rising edge of the serial clock so the external tr...

Page 1065: ...or future device compatibility 15 HCLKRM Receive high frequency clock source bit 0 External receive high frequency clock source from AHCLKR pin 1 Internal receive high frequency clock source from output of programmable high clock divider 14 HCLKRP Receive bitstream high frequency clock polarity select bit 0 Not inverted AHCLKR is not inverted before programmable bit clock divider In the special ca...

Page 1066: ...0 23 22 21 20 19 18 17 16 RTDMS23 RTDMS22 RTDMS21 RTDMS20 RTDMS19 RTDMS18 RTDMS17 RTDMS16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 RTDMS15 RTDMS14 RTDMS13 RTDMS12 RTDMS11 RTDMS10 RTDMS9 RTDMS8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 RTDMS7 RTDMS6 RTDMS5 RTDMS4 RTDMS3 RTDMS2 RTDMS1 RTDMS0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W...

Page 1067: ...erved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 5 RDATA Receive data ready interrupt enable bit 0 Interrupt is disabled A receive data ready interrupt does not generate a McASP receive interrupt RINT 1 Interrupt is enabled A receive data ready interru...

Page 1068: ...eceivers Causes a receive interrupt RINT if this bit is set and RDMAERR in RINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 to this bit has no effect 0 Receive DMA error did not occur 1 Receive DMA error did occur 6 RSTAFRM Receive start of frame flag Causes a receive interrupt RINT if this bit is set and RSTAFRM in RINTCTL is set This bit is cleared by writing a 1 to this...

Page 1069: ... by writing a 1 to this bit Writing a 0 to this bit has no effect 0 Receiver overrun did not occur 1 Receiver overrun did occur 24 1 22 Current Receive TDM Time Slot Registers RSLOT The current receive TDM time slot register RSLOT indicates the current time slot for the receive data frame The RSLOT is shown in Figure 24 55 and described in Table 24 30 Figure 24 55 Current Receive TDM Time Slot Reg...

Page 1070: ... maximum boundary This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high frequency master clock AHCLKR signals have been received If the current counter value is greater than RMAX after counting 32 AHCLKR signals RCKFAIL in RSTAT is set The comparison is performed using unsigned arithmetic 15 8 RMIN 0 FFh Receive clock minimum boundary This 8 ...

Page 1071: ...trol Register REVTCTL 31 16 Reserved A R 0 15 1 0 Reserved A RDATDMA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset A If writing to this field always write the default value for future device compatibility Table 24 32 Receiver DMA Event Control Register REVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the defa...

Page 1072: ...s reset 1 Transmit frame sync generator is active 11 XSMRST Transmit state machine reset enable bit A write to this bit affects the XSMRST bit of GBLCTL 0 Transmit state machine is held in reset 1 Transmit state machine is released from reset 10 XSRCLR Transmit serializer clear enable bit A write to this bit affects the XSRCLR bit of GBLCTL 0 Transmit serializers are cleared 1 Transmit serializers...

Page 1073: ...23 XMASK22 XMASK21 XMASK20 XMASK19 XMASK18 XMASK17 XMASK16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 XMASK15 XMASK14 XMASK13 XMASK12 XMASK11 XMASK10 XMASK9 XMASK8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 XMASK7 XMASK6 XMASK5 XMASK4 XMASK3 XMASK2 XMASK1 XMASK0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset...

Page 1074: ...d always write the default value for future device compatibility 17 16 XDATDLY 0 3h Transmit sync bit delay 0 0 bit delay The first transmit data bit AXR n occurs in same ACLKX cycle as the transmit frame sync AFSX 1h 1 bit delay The first transmit data bit AXR n occurs one ACLKX cycle after the transmit frame sync AFSX 2h 2 bit delay The first transmit data bit AXR n occurs two ACLKX cycles after...

Page 1075: ... Selects whether writes to serializer buffer XRBUF n by way of XBUFn by the CPU EDMA occur through the peripheral configuration port or the DMA port 0 Writes to XRBUF n originate from the DMA port Writes to XRBUF n from the peripheral configuration port are ignored with no effect to the McASP 1 Writes to XRBUF n originate from the peripheral configuration port Writes to XRBUF n from the DMA port a...

Page 1076: ...eld always write the default value for future device compatibility 15 7 XMOD 0 1FFh Transmit frame sync mode select bits 0 Burst mode 1h Reserved 2h 20h 2 slot TDM I2S mode to 32 slot TDM 21h 17Fh Reserved 180h 384 slot DIT mode 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field ...

Page 1077: ...field always write the default value for future device compatibility 7 CLKXP Transmit bitstream clock polarity select bit 0 Rising edge External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock 1 Falling edge External receiver samples data on the rising edge of the serial clock so the transmitter must shift ...

Page 1078: ...or future device compatibility 15 HCLKXM Transmit high frequency clock source bit 0 External transmit high frequency clock source from AHCLKX pin 1 Internal transmit high frequency clock source from output of programmable high clock divider 14 HCLKXP Transmit bitstream high frequency clock polarity select bit 0 Not inverted AHCLKX is not inverted before programmable bit clock divider In the specia...

Page 1079: ... XTDMS26 XTDMS25 XTDMS24 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 23 22 21 20 19 18 17 16 XTDMS23 XTDMS22 XTDMS21 XTDMS20 XTDMS19 XTDMS18 XTDMS17 XTDMS16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 XTDMS15 XTDMS14 XTDMS13 XTDMS12 XTDMS11 XTDMS10 XTDMS9 XTDMS8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 XTDMS7 XTDMS6 XTDMS5 XTDMS4 XTDMS3 XTDMS2 X...

Page 1080: ...eserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 5 XDATA Transmit data ready interrupt enable bit 0 Interrupt is disabled A transmit data ready interrupt does not generate a McASP transmit interrupt XINT 1 Interrupt is enabled A transmit data ready interrupt gene...

Page 1081: ...nsmitters Causes a transmit interrupt XINT if this bit is set and XDMAERR in XINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 has no effect 0 Transmit DMA error did not occur 1 Transmit DMA error did occur 6 XSTAFRM Transmit start of frame flag Causes a transmit interrupt XINT if this bit is set and XSTAFRM in XINTCTL is set This bit is cleared by writing a 1 to this bit W...

Page 1082: ...smitter underrun did occur See Section 24 0 21 6 2 for details on McASP action upon underrun conditions 24 1 34 Current Transmit TDM Time Slot Register XSLOT The current transmit TDM time slot register XSLOT indicates the current time slot for the transmit data frame The XSLOT is shown in Figure 24 67 and described in Table 24 42 Figure 24 67 Current Transmit TDM Time Slot Register XSLOT 31 16 Res...

Page 1083: ... maximum boundary This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high frequency master clock AHCLKX signals have been received If the current counter value is greater than XMAX after counting 32 AHCLKX signals XCKFAIL in XSTAT is set The comparison is performed using unsigned arithmetic 15 8 XMIN 0 FFh Transmit clock minimum boundary This ...

Page 1084: ...ontrol Register XEVTCTL 31 16 Reserved A R 0 15 1 0 Reserved A XDATDMA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset A If writing to this field always write the default value for future device compatibility Table 24 44 Transmitter DMA Event Control Register XEVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the...

Page 1085: ...urrent receive buffer state Always reads 0 when programmed as a transmitter or as inactive If SRMOD bit is set to receive 2h RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF 0 Receive buffer RBUF is empty 1 Receive buffer RBUF contains data and needs to be read before the start of the next time slot or a receiver overrun occurs 4 XRDY Transmit buffer ready bit XRDY indicate...

Page 1086: ... register file in time if a different set of data need to be sent Figure 24 71 DIT Left Channel Status Registers DITCSRA0 DITCSRA5 31 0 DITCSRAn R W 0 LEGEND R W Read Write n value after reset 24 1 39 DIT Right Channel Status Registers DITCSRB0 DITCSRB5 The DIT right channel status registers DITCSRB provide the status of each right channel odd TDM time slot Each of the six 32 bit registers Figure ...

Page 1087: ...he register in time if a different set of data need to be sent Figure 24 73 DIT Left Channel User Data Registers DITUDRA0 DITUDRA5 31 0 DITUDRAn R W 0 LEGEND R W Read Write n value after reset 24 1 41 DIT Right Channel User Data Registers DITUDRB0 DITUDRB5 The DIT right channel user data registers DITUDRB provides the user data of each right channel odd TDM time slot Each of the six 32 bit registe...

Page 1088: ...ers not implemented on a specific DSP may cause improper device operation Figure 24 75 Transmit Buffer Registers XBUFn 31 0 XBUFn R W 0 LEGEND R W Read Write n value after reset 24 1 43 Receive Buffer Registers RBUFn The receive buffers for the serializers RBUF hold data from the serializer before the data goes to the receive format unit For receive operations the RBUF Figure 24 76 is an alias of ...

Page 1089: ...o FIFO AFIFO revision identification register AFIFOREV contains revision data for the Audio FIFO AFIFO The AFIFOREV is shown in Figure 24 77 and described in Table 24 46 Figure 24 77 AFIFO Revision Identification Register AFIFOREV 31 0 REV R 4431 1100h LEGEND R Read only n value after reset Table 24 46 AFIFO Revision Identification Register AFIFOREV Field Descriptions Bit Field Value Description 3...

Page 1090: ...e WLVL field in the Write FIFO status register WFIFOSTS is reset to 0 and pointers are initialized that is the Write FIFO is flushed 1 Write FIFO is enabled If Write FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 WNUMEVT 0 FFh Write word count per DMA event 32 bit When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT transmit DMA event is ...

Page 1091: ...e 24 48 Figure 24 79 Write FIFO Status Register WFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved WLVL R 0 R 0 LEGEND R Read only n value after reset Table 24 48 Write FIFO Status Register WFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 WLVL 0 FFh Write level read only Number of 32 bit words currently in the Write FIFO 0 0 words currently in Write FIFO 1h 1 word cu...

Page 1092: ...it 0 Read FIFO is disabled The RLVL bit in the Read FIFO status register RFIFOSTS is reset to 0 and pointers are initialized that is the Read FIFO is flushed 1 Read FIFO is enabled If Read FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 RNUMEVT 0 FFh Read word count per DMA event 32 bit When the Read FIFO contains at least RNUMEVT words of data then an AREVT receiv...

Page 1093: ...able 24 50 Figure 24 81 Read FIFO Status Register RFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved RLVL R 0 R 0 LEGEND R Read only n value after reset Table 24 50 Read FIFO Status Register RFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RLVL 0 FFh Read level read only Number of 32 bit words currently in the Read FIFO 0 0 words currently in Read FIFO 1h 1 word curr...

Page 1094: ...MMC Secure Digital SD Card Controller Chapter 25 SPRUH91D March 2013 Revised September 2016 Multimedia Card MMC Secure Digital SD Card Controller This chapter describes the multimedia card MMC secure digital SD card controller Topic Page 25 1 Introduction 1095 25 2 Architecture 1096 25 3 Procedures for Common Operations 1112 25 4 Registers 1124 ...

Page 1095: ...ween the MMC SD controller and memory card 512 bit read write FIFO to lower system overhead Signaling to support enhanced direct memory access EDMA transfers slave Maximum clock to MMC varies based on core voltage see your device specific data manual Maximum clock to SD varies based on core voltage see your device specific data manual 25 1 3 Functional Block Diagram The MMC SD card controller tran...

Page 1096: ... SD controller to work as an MMC or SD controller based on the type of card the controller is communicating with Figure 25 2 summarizes the MMC SD mode interface Figure 25 3 illustrates how the controller interfaces to the cards in MMC SD mode In the MMC SD mode the MMC controller supports one or more MMC SD cards Regardless of the number of cards connected the MMC SD controller selects one by usi...

Page 1097: ...nd SD 4 bit mode DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 www ti com Architecture 1097 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 25 3 MMC Configuration and SD Configuration Diagram 25 2 1 Clock Control There are two clocks the function clock and the memory clock ...

Page 1098: ... MMC SD Controller Clocking Diagram 25 2 2 Signal Descriptions Table 25 1 shows the MMC SD controller pins that each mode uses The MMC SD protocol uses the clock command two way communication between the MMC controller and memory card and data MMCSD_DAT0 MMCSD_DAT0 3 or MMCSD_DAT0 7 for MMC card MMCSD_DAT0 or MMCSD_DAT0 3 for SD card pins 1 I input to the MMC controller O output from the MMC contr...

Page 1099: ... sends responses to the command The MMC SD controller requests the card to change states from standby to transfer The card receives the command and sends responses to the command The MMC SD controller sends a write command to the card The card receives the command and sends responses to the command The MMC SD controller sends a block of data to the card The card sends the CRC status to the MMC SD ...

Page 1100: ...nd The MMC SD controller sends a read command to the card The card drives responses to the command The card sends a block of data to the CPU Figure 25 6 MMC SD Mode Read Sequence Timing Diagram Table 25 3 MMC SD Mode Read Sequence Portion of the Sequence Description RD CMD Read command A 6 byte READ_SINGLE_BLOCK command token is sent from the CPU to the card CMD RSP Command response The card sends...

Page 1101: ...ation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller A high level operational description is as follows Data is written to the FIFO through the MMC data transmit register MMCDXR Data is read from the FIFO through the MMC data receive register MMCDRR This is true for both the CPU and EDMA driven transactions however for the EDMA tra...

Page 1102: ...a Card MMC Secure Digital SD Card Controller 25 2 5 Data Flow in the Data Registers MMCDRR and MMCDXR The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register MMCDRR and write 32 bits at a time to the FIFO by writing to the MMC data transmit register MMCDXR However since the memory card is an 8 bit device it transmits or receives one byte at a ti...

Page 1103: ...e FIFO fills up the FIFO controller stops the MMC SD controller from reading any more data until the FIFO is no longer full An EDMA read event generates when the last data arrives as determined by the MMC block length register MMCBLEN and the MMC number of blocks register MMCNBLK settings This EDMA event flushes all of the data that was read from the card to the FIFO Each time an EDMA read event g...

Page 1104: ...ter Increment counter DMA Capture data done DMA No Yes Yes Yes Generate DMA Reset counter Idle DMA pending DMA No done Architecture www ti com 1104 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 25 9 FIFO Operation During Card Read Diagram ...

Page 1105: ...T generates and the DXRDY bit in the MMC status register 0 MMCST0 is also set 25 2 7 2 CPU Writes The system CPU can also directly write the card data by writing the MMC data transmit register MMCDXR The MMC SD peripheral supports writes that are 1 2 3 or 4 bytes wide as shown in Figure 25 8 The CPU makes use of the FIFO to transfer data to the card via the MMC SD controller The CPU writes the dat...

Page 1106: ... Increment counter DMA pending Send data done DMA No Yes Yes Yes Generate DMA Reset counter Idle DMA pending DMA No done Architecture www ti com 1106 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 25 10 FIFO Operation During Card Write Diagram ...

Page 1107: ...MC SD controller The subsections that follow help you decide how to initialize each of control register bits In the MMC SD mode the MMC SD controller must know how wide the data bus must be for the memory card that is connected If an MMC card is connected specify a 1 bit data bus WIDTH 0 in MMCCTL if an SD card is connected specify a 4 bit data bus WIDTH 1 in MMCCTL To place the MMC SD controller ...

Page 1108: ...the size for each block of data transferred between the MMC SD controller and a memory card in MMCBLEN The valid size depends on the type of read write operations A length of 0 bytes is prohibited For multiple block transfers you must specify how many blocks of data are to be transferred between the MMC SD controller and a memory card You can specify an infinite number of blocks by loading 0 into ...

Page 1109: ...to stop reading from the data receive register for a read operation The CPU is also notified of the time out event by an interrupt if the interrupt request is enabled EDATDNE 1 in MMCIM 25 2 9 7 8 Determining When Last Data has Been Written to Card SanDisk SD cards Some SanDisk brand SD cards exhibit a behavior that requires a multiple block write command to terminate with a STOP CMD12 command bef...

Page 1110: ...bit transfer depending on the MMC FIFO control register MMCFIFOCTL setting Performing a write and a read in response to the interrupt generated by the FIFO automatically clears the corresponding interrupt bit flag NOTE You must be aware that an emulation read of the status register clears the interrupt status flags To avoid inadvertently clearing the flag be careful while monitoring MMCST0 via the...

Page 1111: ...A controller Based on the FIFO threshold setting the EDMA event signals generate every time 256 bit or 512 bit data is transferred from the FIFO 25 2 12 Power Management You can put the MMC SD peripheral in reduced power modes to conserve power during periods of low activity The processor power and sleep controller PSC controls the power management of the MMC SD peripheral The PSC acts as a master...

Page 1112: ...e and no response from the cards is expected 2 Use MMCCMD to issue the SEND_OP_CMD CMD1 command with the voltage range supported R3 response if it is successful R1b response if the card is expected to be busy Using MMCCMD to issue the CMD1 command allows the host to identify and reject cards that do not match the VDD range that the host supports 3 If the response in Step 2 is R1b that is the card ...

Page 1113: ...MD0 command puts all cards MMC and SD in the idle state and no response from the cards is expected 2 Use MMCCMD to issue the APP_CMD CMD55 command R1 response is expected to indicate that the command that follows is an application command 3 Use MMCCMD to send the SD_SEND_OP_COND ACMD41 command with the voltage range supported R3 response is expected to SD cards Using MMCCMD to send the ACMD41 comm...

Page 1114: ... CMD3 RCA in R6 Response Command CMD2 CID in R2 ALL_SEND_CID Response Command Procedures for Common Operations www ti com 1114 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller 6 Repeat Step 4 and Step 5 to identify and retrieve relative addresses from all remaining SD ca...

Page 1115: ... s maximum block length 5 Use MMCCMD to send the SET_BLOCKLEN command if the block length is different than the length used in the previous operation The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD 6 Reset the FIFO FIFORST bit in MMCFIFOCTL 7 Set the FIFO direction to transmit FIFODIR bit in MMCFIFOCTL 8 Set the access width ACCWD bits i...

Page 1116: ... the transfer Start writing one block of data Only 512 byte block length is permitted Is CRCWR 1 Is DATDNE 1 Is DXRDY 1 Check CRCWR bit for any write CRC errors Check DATDNE bit to see if the transfer is done If not then Check DXRDY bit to see the data transmit register is ready for the next byte Load the data transmit register with the next byte Procedures for Common Operations www ti com 1116 SP...

Page 1117: ...or errors 25 3 4 MMC SD Mode Single Block Read Operation Using the CPU To perform a single block read the same block length must be set in both the MMC SD controller and the card The procedure for this operation is as follows 1 Write the card s relative address to the MMC argument registers MMCARGH and MMCARGL Load the high part of the address to MCARGH and the low part of the address to MMCARGL 2...

Page 1118: ...CRCRD 1 Is DRRDY 1 Is DATDNE 1 Is TOUTRD 1 Check TOUTRD bit to verify that read operation has not timed out Check CRCRD bit for any read CRC errors Check DATDNE bit to see if transfer is done If not then Check DRRDY bit to see the data receive register has received a new byte Read the new byte from the data receiver register Procedures for Common Operations www ti com 1118 SPRUH91D March 2013 Revi...

Page 1119: ...ation Using CPU NOTE This procedure uses a STOP_TRANSMISSION command to end the block transfer This assumes that the value in the MMC number of blocks counter register MMCNBLK is 0 A multiple block operation terminates itself if you load MMCNBLK with the exact number of blocks you want transferred To perform a multiple block write the same block length needs to be set in both the MMC SD controller...

Page 1120: ...ommand register Check CRCWR bit for any write CRC errors Check DXRDY to see if a new byte can be put in MMCDXR register STOP_TRANSMISSION COMMAND Terminate the multiple block write operation Procedures for Common Operations www ti com 1120 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital S...

Page 1121: ...k for errors 13 Use MMCCMD to send the STOP_TRANSMISSION command 25 3 8 MMC SD Mode Multiple Block Read Operation Using CPU NOTE This procedure uses a STOP_TRANSMISSION command to end the block transfer This assumes that the value in the MMC number of blocks counter register MMCNBLK is 0 A multiple block operation terminates itself if you load MMCNBLK with the exact number of blocks you want trans...

Page 1122: ...o verify that the read operation has not timed out Check CRCRD bit for any read CRC errors Check DRRDY to see if a new byte is in the data STOP_TRANSMISSION COMMAND Terminate the multiple block read operation Is TOUTRD 1 receive register Procedures for Common Operations www ti com 1122 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments In...

Page 1123: ...e DMATRIG bit in MMCCMD to trigger the first data transfer 11 Wait for DMA sequence to complete 12 Use the MMC status register 0 MMCST0 to check for errors 13 Use MMCCMD to send the STOP_TRANSMISSION command 25 3 10 SDIO Card Function To support the SDIO card the following features are available in the MMC SD controller Read wait operation request Interrupt to CPU at the start of read wait operati...

Page 1124: ...gister Section 25 4 1 4h MMCCLK MMC Memory Clock Control Register Section 25 4 2 8h MMCST0 MMC Status Register 0 Section 25 4 3 Ch MMCST1 MMC Status Register 1 Section 25 4 4 10h MMCIM MMC Interrupt Mask Register Section 25 4 5 14h MMCTOR MMC Response Time Out Register Section 25 4 6 18h MMCTOD MMC Data Read Time Out Register Section 25 4 7 1Ch MMCBLEN MMC Block Length Register Section 25 4 8 20h ...

Page 1125: ...t Field Value Description 31 11 Reserved 0 Reserved 10 PERMDX Endian select when writing 0 Little endian is selected 1 Big endian is selected 9 PERMDR Endian select when reading 0 Little endian is selected 1 Big endian is selected 8 WIDTH1 0 3h Data bus width 1 MMC mode only Used in conjunction with the WIDTH0 bit 0 Data bus has 1 bit only MMCSD_DAT0 is used 1h Data bus has 4 bits only MMCSD_DAT0 ...

Page 1126: ... 25 2 1 The MMC memory clock control register MMCCLK is shown in Figure 25 18 and described in Table 25 7 Figure 25 18 MMC Memory Clock Control Register MMCCLK 31 16 Reserved R 0 15 10 9 8 7 0 Reserved DIV4 CLKEN CLKRT R 0 R W 0 R W 0 R W FFh LEGEND R W Read Write R Read only n value after reset Table 25 7 MMC Memory Clock Control Register MMCCLK Field Descriptions Bit Field Value Description 31 1...

Page 1127: ... command with BSYEXP bit otherwise it continues transferring data 2 Bit 12 TRNDNE indicates that the last byte of a transfer has been completed Bit 0 DATDNE occurs at end of a transfer but not until the CRC check and programming has completed Figure 25 19 MMC Status Register 0 MMCST0 31 16 Reserved R 0 15 14 13 12 11 10 9 8 Reserved CCS TRNDNE DATED DRRDY DXRDY Reserved R 0 R 0 R 0 RC 0 R 0 R 1 R ...

Page 1128: ...en detected 1 A response CRC error has been detected 6 CRCRD Read data CRC error 0 A read data CRC error has not been detected 1 A read data CRC error has been detected 5 CRCWR Write data CRC error 0 A write data CRC error has not been detected 1 A write data CRC error has been detected 4 TOUTRS Response time out event 0 A response time out event has not occurred 1 A time out event has occurred wh...

Page 1129: ...1 FIFO is empty 4 DAT3ST MMCSD_DAT3 status 0 The signal level on the MMCSD_DAT3 pin is a logic low level 1 The signal level on the MMCSD_DAT3 pin is a logic high level 3 DRFUL Data receive register MMCDRR is full 0 A data receive register full condition is not detected The data receive shift register is not full 1 A data receive register full condition is detected The data receive shift register i...

Page 1130: ...eld Value Description 31 14 Reserved 0 Reserved 13 ECCS Command completion signal interrupt enable 0 Command completion signal interrupt is disabled 1 Command completion signal interrupt is enabled 12 ETRNDNE Transfer done TRNDNE interrupt enable 0 Transfer done interrupt is disabled 1 Transfer done interrupt is enabled 11 EDATED MMCSD_DAT3 edge detect DATED interrupt enable 0 MMCSD_DAT3 edge dete...

Page 1131: ...interrupt is disabled 1 Response time out event interrupt is enabled 3 ETOUTRD Read data time out event TOUTRD interrupt enable 0 Read data time out event interrupt is disabled 1 Read data time out event interrupt is enabled 2 ERSPDNE Command response done RSPDNE interrupt enable 0 Command response done interrupt is disabled 1 Command response done interrupt is enabled 1 EBSYDNE Busy done BSYDNE i...

Page 1132: ...an MMCTOR can provide a software time out mechanism can be implemented The MMC response time out register MMCTOR is shown in Figure 25 22 and described in Table 25 11 Figure 25 22 MMC Response Time Out Register MMCTOR 31 18 17 16 Reserved TOD_25_16 R 0 R W 0 15 8 7 0 TOD_25_16 TOR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 25 11 MMC Response Time Out Register MMCTOR Fi...

Page 1133: ...is set in MMCST0 If a memory card should require a longer time out period than MMCTOD can provide a software time out mechanism can be implemented The MMC data read time out register MMCTOD is shown in Figure 25 23 and described in Table 25 12 Figure 25 23 MMC Data Read Time Out Register MMCTOD 31 16 Reserved R 0 15 0 TOD_15_0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 25 12...

Page 1134: ... 25 24 and described in Table 25 13 NOTE The BLEN bits value must be the same as the CSD register settings in the MMC SD card To be precise it should match the value of the READ_BL_LEN field for read or WRITE_BL_LEN field for write Figure 25 24 MMC Block Length Register MMCBLEN 31 16 Reserved R 0 15 12 11 0 Reserved BLEN R 0 R W 200h LEGEND R W Read Write R Read only n value after reset Table 25 1...

Page 1135: ...0 Infinite number of blocks The MMC controller reads writes blocks of data until a STOP_TRANSMISSION command is written to the MMC command register MMCCMD 1h FFFFh n blocks The MMC controller reads writes only n blocks of data even if the STOP_TRANSMISSION command has not been written to the MMC command register MMCCMD 25 4 10 MMC Number of Blocks Counter Register MMCNBLC The MMC number of blocks ...

Page 1136: ...RR R W 0 LEGEND R W Read Write n value after reset Table 25 16 MMC Data Receive Register MMCDRR Field Descriptions Bit Field Value Description 31 0 DRR 0 FFFF FFFFh Data receive 25 4 12 MMC Data Transmit Register MMCDXR The MMC data transmit register MMCDXR is used for storing the data to be transmitted from the MMC controller to the memory card The CPU or the DMA controller can write data to this...

Page 1137: ...ommand Register MMCCMD 31 24 Reserved R 0 23 17 16 Reserved DMATRIG R 0 R W 0 15 14 13 12 11 10 9 8 DCLR INITCK WDATX STRMTP DTRW RSPFMT BSYEXP R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 0 PPLEN Reserved CMD R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 25 18 MMC Command Register MMCCMD Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 D...

Page 1138: ...ansfer is a write operation 10 9 RSPFMT 0 3h Response format expected type of response to the command 0 No response 1h R1 R4 R5 or R6 response 48 bits with CRC 2h R2 response 136 bits with CRC 3h R3 response 48 bits with no CRC 8 BSYEXP Busy expected If an R1b R1 with busy response is expected set RSPFMT 1h and BSYEXP 1 0 A busy signal is not expected 1 A busy signal is expected 7 PPLEN Push pull ...

Page 1139: ... causes the MMC controller to send a command therefore MMCARGHL must be configured before writing to MMCCMD The content of MMCARGHL is kept after the transfer to the shift register however modification to MMCARGHL is not allowed during a sending operation For the format of a command see Figure 25 30 and Table 25 19 The MMC argument register MMCARGHL is shown in Figure 25 31 and described in Table ...

Page 1140: ...se registers holds up to 16 bits Table 25 21 and Table 25 22 show the format for each type of response and which MMC response registers are used for the bits of the response The first byte of the response is a command index byte and is stored in the MMC command index register MMCCIDX Figure 25 32 MMC Response Register 0 and 1 MMCRSP01 31 16 MMCRSP1 R W 0 15 0 MMCRSP0 R W 0 LEGEND R W Read Write n ...

Page 1141: ... 1 Bits 7 0 of the response are stored to bits 7 0 of MMCRSP5 Table 25 21 R1 R3 R4 R5 or R6 Response 48 Bits Bit Position of Response Register 47 40 MMCCIDX 39 24 MMCRSP7 23 8 MMCRSP6 7 0 MMCRSP5 1 MMCRSP4 0 Table 25 22 R2 Response 136 Bits Bit Position of Response Register 135 128 MMCCIDX 127 112 MMCRSP7 111 96 MMCRSP6 95 80 MMCRSP5 79 64 MMCRSP4 63 48 MMCRSP3 47 32 MMCRSP2 31 16 MMCRSP1 15 0 MMC...

Page 1142: ...rite operation see Section 25 2 3 1 the CRC status token is stored in DRSP 25 4 17 MMC Command Index Register MMCCIDX The MMC command index register MMCCIDX stores the first byte of a response from a memory card Table 25 21 and Table 25 22 show the format for each type of response The MMC command index register MMCCIDX is shown in Figure 25 37 and described in Table 25 24 Figure 25 37 MMC Command ...

Page 1143: ...e 25 25 SDIO Control Register SDIOCTL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 RDWTCR Read wait enable for CRC error To end the read wait operation write 0 to RDWTRQ No need to clear RDWTCR 0 Read wait is disabled 1 Automatically start read wait on CRC error detection during multiple block read access and not the last block to be transferred RDWTRQ is automatically...

Page 1144: ... SDIOST0 31 16 Reserved R 0 15 3 2 1 0 Reserved RDWTST INTPRD DAT1 R 0 R 0 R 0 R 1 LEGEND R W Read Write R Read only n value after reset Table 25 26 SDIO Status Register 0 SDIOST0 Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 RDWTST Read wait status 0 Read wait operation not in progress 1 Read wait operation in progress 1 INTPRD Interrupt period 0 Interrupt not in progr...

Page 1145: ...le 0 SDIO card interrupt is disabled 1 SDIO card interrupt is enabled 25 4 21 SDIO Interrupt Status Register SDIOIST The SDIO interrupt status register SDIOIST is shown in Figure 25 41 and described in Table 25 28 Figure 25 41 SDIO Interrupt Status Register SDIOIST 31 16 Reserved R 0 15 2 1 0 Reserved RWS IOINT R 0 R W1C 0 R W1C 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 ha...

Page 1146: ...trol Register MMCFIFOCTL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 ACCWD 0 3h Access width Used by FIFO control to determine full empty flag 0 CPU EDMA access width of 4 bytes 1h CPU EDMA access width of 3 bytes 2h CPU EDMA access width of 2 bytes 3h CPU EDMA access width of 1 byte 2 FIFOLEV FIFO level Sets the threshold level that determines when the EDMA request...

Page 1147: ...dback Copyright 2013 2016 Texas Instruments Incorporated Real Time Clock RTC Chapter 26 SPRUH91D March 2013 Revised September 2016 Real Time Clock RTC This chapter describes the real time clock RTC Topic Page 26 1 Introduction 1148 26 2 Architecture 1149 26 3 Registers 1155 ...

Page 1148: ...ot interfere with the accuracy of the time and date Alarms are available to interrupt the CPU at a particular time or at periodic time intervals such as once per minute or once per day In addition the RTC can interrupt the CPU every time the calendar and time registers are updated or at programmable periodic intervals 26 1 2 Features The real time clock RTC provides the following features 100 year...

Page 1149: ...riven with a 32 768 kHz reference clock or RTC_XI and RTC_XO can be connected to an external crystal This signal is the input to the RTC internal oscillator RTC_XO O RTC time base output signal RTC_XO is the output from the RTC internal oscillator If a crystal is not used as the time base for RTC_XI RTC_XO should be left unconnected 26 2 3 Isolated Power Supply The RTC has a power supply that is i...

Page 1150: ...When HOURMODE 1 12 hour mode is selected The hours are represented as 00 through 12 MERIDIEM 0 indicates ante meridiem AM and MERIDIEM 1 indicates post meridiem PM 26 2 4 1 3 Reading from Time Calendar Registers The time calendar registers are updated every second as the time changes During a read of the SECOND register the RTC copies the current values of the time date registers into shadow read ...

Page 1151: ...following registers while RTC is running SECOND MINUTE HOUR DAY MONTH YEAR DOTW ALARMSECOND when ALARM interrupt is enabled ALARMMINUTE when ALARM interrupt is enabled ALARMHOUR when ALARM interrupt is enabled ALARMDAY when ALARM interrupt is enabled ALARMMONTH when ALARM interrupt is enabled ALARMYEAR when ALARM interrupt is enabled CTRL SET32COUNTER field only the other fields in CTRL do not req...

Page 1152: ...upt request to the CPU When the device is initially powered on the RTC may issue spurious interrupt signals to the CPU To avoid issues a software reset should be performed on the RTC module before the CPU interrupt controller is initialized See Section 26 2 10 for more information on reset considerations 26 2 5 1 Alarm Interrupt Enable and Status Bits The ALARM bit in the interrupt register INTERR...

Page 1153: ...MM SS format transitions from 23 59 59 to 00 00 00 the STATUS register sets all four periodic status bits DAYEVT HREVT MINEVT and SECEVT because all four time periods were incremented These bits all remain high until 1 The TIME bit is cleared and all four status bits clear to zero until TIME is set again OR 2 The current time reaches 00 00 01 At that point the SECEVT remains set while the DAYEVT H...

Page 1154: ...igured and enabled If the RTC is unintentionally powered down the value written to the SCRATCH register is cleared 26 2 8 Real Time Clock Response to Low Power Modes Idle Configurations The device is divided into idle domains that can be programmed to be idle or active The state of all domains is called the idle configuration The RTC runs on its own external clock source and is not affected by any...

Page 1155: ... 20h ALARMSECOND Alarm Seconds Register Section 26 3 8 24h ALARMMINUTE Alarm Minutes Register Section 26 3 9 28h ALARMHOUR Alarm Hours Register Section 26 3 10 2Ch ALARMDAY Alarm Days Register Section 26 3 11 30h ALARMMONTH Alarm Months Register Section 26 3 12 34h ALARMYEAR Alarm Years Register Section 26 3 13 40h CTRL Control Register Section 26 3 14 44h STATUS Status Register Section 26 3 15 48...

Page 1156: ... Reserved 0 Reserved 6 4 SEC1 0 5h Most significant digit of second value Range for SEC1 SEC0 is 00 59 3 0 SEC0 0 9h Least significant digit of second value Range for SEC1 SEC0 is 00 59 26 3 2 Minute Register MINUTE NOTE Out of reset the minute register MINUTE is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 26 2 6 The minute register ...

Page 1157: ...are encoded with their binary equivalent The HOUR register is shown in Figure 26 6 and described in Table 26 5 Figure 26 6 Hour Register HOUR 31 16 Reserved R 0 15 8 7 6 5 4 3 0 Reserved MERIDIEM Rsvd HOUR1 HOUR0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 5 Hour Register HOUR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 MER...

Page 1158: ...Reserved 5 4 DAY1 0 3h Most significant digit of day of the month value Range for DAY1 DAY0 is 01 31 3 0 DAY0 0 9h Least significant digit of day of the month value Range for DAY1 DAY0 is 01 31 26 3 5 Month Register MONTH NOTE Out of reset the month register MONTH is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 26 2 6 The month regist...

Page 1159: ...d Value Description 31 8 Reserved 0 Reserved 7 4 YEAR1 0 9h Most significant digit of years value Range for YEAR1 YEAR0 is 00 99 3 0 YEAR0 0 9h Least significant digit of years value Range for YEAR1 YEAR0 is 00 99 26 3 7 Day of the Week Register DOTW NOTE Out of reset the day of the week register DOTW is write protected To disable write protection correct keys must be written to the KICKnR registe...

Page 1160: ...served 6 4 SEC1 0 5h Most significant digit of alarm seconds value Range for SEC1 SEC0 is 00 59 3 0 SEC0 0 9h Least significant digit of alarm seconds value Range for SEC1 SEC0 is 00 59 26 3 9 Alarm Minute Register ALARMMINUTE NOTE Out of reset the alarm minute register ALARMMINUTE is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 26 2 ...

Page 1161: ... 9 are encoded with their binary equivalent The ALARMHOUR register is shown in Figure 26 13 and described in Table 26 12 Figure 26 13 Alarm Hour Register ALARMHOUR 31 16 Reserved R 0 15 8 7 6 5 4 3 0 Reserved MERIDIEM Rsvd HOUR1 HOUR0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 12 Alarm Hour Register ALARMHOUR Field Descriptions Bit Field Value Descript...

Page 1162: ...larm interrupt Days are stored as binary coded decimal BCD format In BCD format the decimal numbers 0 through 9 are encoded with their binary equivalent The ALARMDAYS register is shown in Figure 26 14 and described in Table 26 13 Figure 26 14 Alarm Day Register ALARMDAY 31 16 Reserved R 0 15 6 5 4 3 0 Reserved DAY1 DAY0 R 0 R W 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 26...

Page 1163: ... 31 5 Reserved 0 Reserved 4 MONTH1 0 1h Most significant digit of months value For MONTH1 MONTH0 JAN 01 and DEC 12 3 0 MONTH0 0 9h Least significant digit of months value For MONTH1 MONTH0 JAN 01 and DEC 12 26 3 13 Alarm Year Register ALARMYEAR NOTE Out of reset the alarm year register ALARMYEAR is write protected To disable write protection correct keys must be written to the KICKnR registers see...

Page 1164: ...split power 1 Enable split power 6 RTCDISABLE Disable RTC module and gate 32 kHz reference clock RTC should only be disabled using this bit if the module will never be used and saving power is desired 0 RTC is functional 1 RTC is disabled and 32 kHz reference clock is gated 5 SET32COUNTER Set the 32 kHz counter with the value stored in the compensation registers when the SET32COUNTER bit is set RT...

Page 1165: ...time update 0 DAYS register did not increment during the last time update 1 DAYS register incremented during the last time update 4 HREVT When the TIMER 1 in the INTERRUPTS register HREVT indicates if the HOURS register incremented during the most recent time update 0 HOURS register did not increment during the last time update 1 HOURS register incremented during the last time update 3 MINEVT When...

Page 1166: ... R 0 15 4 3 2 1 0 Reserved ALARM TIMER EVERY R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 18 Interrupt Register INTERRUPT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 ALARM Enable interrupt generation for when the alarm time and date match the current time and date 0 Alarm interrupt is disabled 1 Alarm interrupt is enabled 2 TIME...

Page 1167: ...llator compensation value The AUTOCOMP bit in the control register CTRL must be enabled for compensation to take place The COMPLSB register is shown in Figure 26 20 and described in Table 26 19 Figure 26 20 Compensation LSB Register COMPLSB 31 16 Reserved R 0 15 8 7 0 Reserved COMPLSB R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 19 Compensations Register COMPLSB Field D...

Page 1168: ...llator compensation value The AUTOCOMP bit in the control register CTRL must be enabled for compensation to take place The COMPMSB register is shown in Figure 26 21 and described in Table 26 20 Figure 26 21 Compensation MSB Register COMPMSB 31 16 Reserved R 0 15 8 7 0 Reserved COMPMSB R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 20 Compensations Register COMPMSB Field D...

Page 1169: ...d described in Table 26 21 Figure 26 22 Oscillator Register OSC 31 16 Reserved R 0 15 6 5 4 0 Reserved SWRESET Reserved R 0 W 0 R W 7h LEGEND R W Read Write R Read only W Write only n value after reset Table 26 21 Oscillator Register OSC Field Descriptions Bit Field Value Description 31 6 Reserved 0 Reserved 5 SWRESET Software reset Always reads back 0 0 No action 1 Reset RTC module and registers ...

Page 1170: ...ers SCRATCHn Field Descriptions Bit Field Value Description 31 0 SCRATCHn 0 FFFF FFFFh General purpose 32 bit registers that have no effect on RTC functionality 26 3 21 Kick Registers KICK0R KICK1R The kick registers KICKnR are used to enable and disable write protection on the RTC registers Out of reset the RTC registers are write protected To disable write protection correct keys must be written...

Page 1171: ...pheral Interface SPI Chapter 27 SPRUH91D March 2013 Revised September 2016 Serial Peripheral Interface SPI This chapter describes the serial peripheral interface SPI module See your device specific data manual to determine how many SPIs are available on your device Topic Page 27 1 Introduction 1172 27 2 Architecture 1174 27 3 Registers 1200 ...

Page 1172: ... SPIEMU 16 bit Transmit data register SPIDAT0 and 16 bit Transmit data and format selection register SPIDAT1 8 bit baud clock generator Serial clock SPIx_CLK I O pin Slave in master out SPIx_SIMO I O pin Slave out master in SPIx_SOMI I O pin SPI enable SPIx_ENA I O pin 4 pin or 5 pin mode only Multiple slave chip select SPIx_SCS n I O pins 4 pin or 5 pin mode only Programmable SPI clock frequency ...

Page 1173: ... the SPI block diagram Figure 27 1 SPI Block Diagram NOTE The value x indicates the applicable SPI that is SPI0 SPI1 etc See your device specific data manual to determine how many SPIs are available on your device The value n indicates the SPI pins available See your device specific data manual to determine how many SPI pins are available on your device A Indicates the log controlled by SPI regist...

Page 1174: ...Ix_SIMO Input Output Serial data input in slave mode serial data output in master mode SPIx_SOMI Input Output Serial data output in slave mode serial data input in master mode SPIx_CLK Input Output Serial clock input in slave mode serial clock output in master mode SPIx_SCS n 2 Input Output Slave chip select output in master mode input in slave mode SPIx_ENA Input Output Input in master mode outpu...

Page 1175: ...tion of data on the I O pins Section 27 3 7 1Ch SPIPC2 Pin control register 2 Reflects the values on the I O pins Section 27 3 8 20h SPIPC3 Pin control register 3 Controls the values sent to the I O pins Section 27 3 9 24h SPIPC4 Pin control register 4 Sets data values in the SPIPC3 register Section 27 3 10 28h SPIPC5 Pin control register 5 Clears values in the SPIPC3 register Section 27 3 11 38h ...

Page 1176: ... 0 0 0 0 SPIGCR1 CLKMOD 1 1 1 1 SPIGCR1 MASTER 1 1 1 1 SPIPC0 SOMIFUN 1 1 1 1 SPIPC0 SIMOFUN 1 1 1 1 SPIPC0 CLKFUN 1 1 1 1 SPIPC0 ENAFUN 0 0 1 1 SPIPC0 SCS0FUN 0 1 0 1 Table 27 4 Allowed SPI Register Settings in Master Modes Register Bit s Master 3 pin Master 4 pin Chip Select Master 4 pin Enable Master 5 pin SPIINT0 ENABLEHIGHZ 0 1 0 1 0 1 0 1 SPIFMTn WDELAY 0 to 3Fh 0 to 3Fh 0 to 3Fh 0 to 3Fh SP...

Page 1177: ...that if SPIDELAY T2CDELAY 0 then the T2CDELAY period 0 If the PHASE bit in the SPI data format register n SPIFMTn is 0 then the T2CDELAY period lasts for an additional 1 2 SPIx_CLK time over that specified by the above equation The current value of the CSHOLD bit in the SPI transmit data register SPIDAT1 must be cleared to 0 for T2C delay to be enabled NOTE If the SPIDAT1 CSHOLD bit is set within ...

Page 1178: ...n certain cases the allowed values may still be ignored For complete details on each mode see the following sections that explain the SPI operation for each of the slave modes Table 27 5 SPI Register Settings Defining Slave Modes Register Bit s Slave 3 pin Slave 4 pin Chip Select Slave 4 pin Enable Slave 5 pin SPIGCR0 RESET 1 1 1 1 SPIGCR1 ENABLE 1 1 1 1 SPIGCR1 LOOPBACK 0 0 0 0 SPIGCR1 CLKMOD 0 0...

Page 1179: ...both must be programmed to 1 to configure the SPI for master mode or to 0 to configure the SPI for slave mode The SPI bus master is the device that drives the SPIx_CLK signal and initiates SPI bus transfers In SPI master mode the SPIx_SOMI pin output buffer is in a high impedance state and the SPIx_CLK and the SPIx_SIMO pin output buffer is enabled In SPI slave mode the SPIx_SIMO and SPIx_CLK pin ...

Page 1180: ...te and the SPIx_CLK SPIx_SIMO and SPIx_SCS n pin output buffer is enabled In SPI slave mode the SPIx_CLK SPIx_SIMO and SPIx_SCS n pin output buffer is in a high impedance state and the SPIx_SOMI pin output buffer is enabled when SPIx_SCS n is asserted and in a high impedance state when SPIx_SCS n is deasserted In slave mode with the chip select option enabled the SPI ignores all transactions on th...

Page 1181: ...it Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 27 3 SPI 4 Pin Option with SPIx_SCS n NOTE During an SPI transfer if the slave mode SPI detects a deassertion of its chip select even before its internal character length counter overflows then it 3 states its SPIx_SOMI pin Once this condition has occurred if a SPIx_CLK edge is detec...

Page 1182: ...orks this way After a transfer completes both the master and slave SPI modules need to be serviced The slave SPI deasserts SPIx_ENA after the transfer indicating it requires servicing and is not ready The slave should begin servicing its SPI by first reading receive data from the SPI receive buffer register SPIBUF Next the slave device should write transmit data to the SPI transmit data registers ...

Page 1183: ...IMO Master MASTER 1 CLKMOD 1 SPIBUF SPIDAT1 CPU DMA write CPU DMA read SPIDAT1 SPIBUF CPU DMA read CPU DMA write SPIx_ENA SPIx_ENA www ti com Architecture 1183 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 27 4 SPI 4 Pin Option with SPIx_ENA ...

Page 1184: ...is enabled and disabled asynchronously by the SPIx_SCS n input and the SPIx_ENA pin output buffer enable depends upon the status of the transmit buffer and the state of the SPIx_SCS n input In SPI slave mode the assertion of the SPIx_ENA pin by the slave is delayed until the master asserts SPIx_SCS n thereby allowing multiple SPI slaves on a single SPI bus each slave with its own enable pin If the...

Page 1185: ... 5 Pin Option with SPIx_ENA and SPIx_SCS n NOTE Push Pull mode of the SPIx_ENA pin can be used only when there is a single slave in the system When there are multiple SPI slave devices connected to the common SPIx_ENA pin all the slaves should configure their SPIx_ENA pins in high impedance mode During an SPI transfer if slave mode SPI detects a deassertion of its chip select even before its inter...

Page 1186: ...by the SPIFMTn CHARLEN bit Legal values are 2 bits 2h to 16 bits 10h The character length is independently configured for each of the four data formats and it must be programmed in both master mode and slave mode Transmit data is written to SPIDAT1 The transmit data must be written right justified irrespective of the character length The SPI automatically sends out the data correctly based on the ...

Page 1187: ...SPIDAT1 is written and before the first edge of SPIx_CLK The data input and output edges depend on the values of both the POLARITY and PHASE bits as shown in Table 27 7 Table 27 7 Clocking Modes POLARITY PHASE Action 0 0 Data is output on the rising edge of SPIx_CLK Input data is latched on the falling edge 0 1 Data is output one half cycle before the first rising edge of SPIx_CLK and on subsequen...

Page 1188: ...SPIx_CLK A write to the SPIDAT register starts SPIx_CLK Clock polarity 1 Clock phase 0 1 2 3 4 5 6 7 8 LSB D1 D2 D3 D4 D5 D6 MSB D0 D1 D2 D3 D4 D5 D6 D7 Write SPIDAT SPIx CLK _ SPIx SIMO _ SPIx_SOMI Sample in reception Clock phase 1 SPIx_CLK with delay Data is output one half cycle before the first rising of SPI CLK and on subsequent falling edges of SPI CLK Input data is latched on the rising edg...

Page 1189: ... a character length of five bits Figure 27 12 Five Bits per Character 5 Pin Option 27 2 12 Interrupt Support The SPI interrupt system is controlled by three registers The SPI interrupt level register SPILVL controls the interrrupt level The interrupt level must be set to select the level one interrupt INT1 The SPI interrupt register SPIINT contains bits to selectively enable disable each interrupt...

Page 1190: ...y the SPI master continually monitors the bus for faults on its data line The handshaking between master and slave can be monitored as well and appropriate actions can be taken interrupt timeout when the handshake breaks down The following sections describe these robustness features in more detail 27 2 14 1 SPI Internal Loopback Test Mode Master Only CAUTION The internal loop back self test mode s...

Page 1191: ...lave device does not deassert the SPIx_ENA signal before the T2EDELAY timeout value expires the SPIFLG DESYNC flag is set and a desynchronization interrupt is asserted if enabled The T2E delay period does not always complete sometimes it is skipped or terminated early The T2E delay period terminates immediately after the SPIx_ENA input is sampled using the SPI module clock at intervals of SPIFMTn ...

Page 1192: ...will be generated only if the SPIx_SCS n pin is configured as a functional pin 27 2 15 Reset Considerations This section describes the software and hardware reset considerations 27 2 15 1 Software Reset Considerations The SPI module contains a software reset RESET bit in the SPI global control register 0 SPIGCR0 that is used to reset the SPI module As a result of a reset the SPI module register va...

Page 1193: ...dule does not support soft or hard stop during emulation breakpoints The SPI module will continue to run if an emulation breakpoint is encountered In addition any status registers that are cleared after reading will be affected if viewed in a memory or watch window of the debugger since the emulator will read these registers to update the value displayed in the window 27 2 19 Initialization Perfor...

Page 1194: ...lustrating the C2TDELAY C2EDELAY T2CDELAY T2EDELAY and WDELAY delays and their interaction with the SPIx_SCS n and SPIx_ENA pins for all SPI modes 27 2 20 1 SPI 3 Pin Mode Figure 27 13 illustrates the WDELAY option in SPI 3 pin master mode This is the only delay available in this mode In CASE1 a new transfer is initiated during the WDELAY period and the transfer begins immediately after the WDELAY...

Page 1195: ...erted during the T2EDELAY period Consequently the T2EDELAY period is terminated early a and the WDELAY period begins immediately b if enabled The next transfer is initiated as soon as the slave asserts SPIx_ENA again In CASE2 the T2EDELAY period c completes before the SPIx_ENA is deasserted As a result the DESYNC error is set However since the SPIx_ENA is deasserted during the WDELAY period d the ...

Page 1196: ... error set SPI CLK i x_ SPI CLK ii x_ SPI CLK iii x_ SPI CLK iv x_ SPI ENA x_ e T2EDELAY f WDELAY Deasserted Case 3 Desync error set Deasserted Architecture www ti com 1196 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 27 15 SPI 4 Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WD...

Page 1197: ...d then the DESYNC error is not set The SPI master behavior in this case depends on whether the SPIx_ENA gets deasserted during the T2CDELAY period CASE1 WDELAY period CASE3 or after the WDELAY period completes CASE4 If the slave deasserts the SPIx_ENA signal before the completion of the configured master delays T2CDELAY T2EDELAY WDELAY then the master delays the next transfer until the slave asser...

Page 1198: ...PIx_ENA f T2CDELAY g T2EDELAY Case 3 Deasserted SPIx_SCS n h WDELAY Desync error set SPIx_CLK i SPIx_CLK ii SPIx_CLK iii SPIx_CLK iv SPIx_ENA j T2CDELAY k T2EDELAY Case 4 Deasserted SPIx_SCS n m WDELAY Desync error set Architecture www ti com 1198 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface ...

Page 1199: ...SCS n x_ SPI ENA x_ d C2EDELAY f C2TDELAY Deasserted Pol 0 Ph 0 Pol 0 Ph 1 Pol 1 Ph 0 Pol 1 Ph 1 SPI CLK x_ Case 3 SPI CLK x_ SPI CLK x_ SPI CLK x_ SPI SCS n x_ SPI ENA x_ g C2EDELAY Deasserted Timeout error set www ti com Architecture 1199 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Fig...

Page 1200: ...r 5 Clear SPIPC3 Section 27 3 11 38h SPIDAT0 SPI Data Transmit Register 0 Section 27 3 12 3Ch SPIDAT1 SPI Data Transmit Register 1 Data Transmit and Format Select Section 27 3 13 40h SPIBUF SPI Receive Buffer Register Section 27 3 14 44h SPIEMU SPI Receive Emulation Register Section 27 3 15 48h SPIDELAY SPI Delay Register Section 27 3 16 4Ch SPIDEF SPI Default Chip Select Register Section 27 3 17 ...

Page 1201: ... get dropped When ENABLE bit is cleared to 0 the following SPI registers get forced to their default states to 0s except for RXEMPTY bit in SPIBUF Both TX and RX shift registers The TXDATA fields of SPIDAT0 and SPIDAT1 registers All the fields of the SPIFLG register Contents of SPIBUF and the internal RXBUF registers 0 SPI is not activated for transfers 1 Activates SPI 23 17 Reserved 0 Reads retur...

Page 1202: ... 0 SLAVE MODE SPIx_CLK is an input from the master who initiates the transfers Data is transmitted on the SPIx_SOMI pin and received on the SPIx_SIMO pin The SPIx_SCS n pin is an input pin if configured as SPI slave chip select The SPIx_ENA pin is an output pin if configured as the SPI enable pin 1h 2h Reserved 3h MASTER MODE SPIx_CLK is an output and the SPI initiates transfers Data is transmitte...

Page 1203: ...Enables the DMA request signal to be generated for both receive and transmit channels Set DMAREQEN only after setting the SPIGCR1 ENABLE bit to 1 0 DMA is not used 1 DMA requests will be generated Note A transmit DMA request will be generated each time a transmit data is copied to the shift register either from TXBUF or directly from SPIDAT0 SPIDAT1 Note A receive DMA request will be generated eac...

Page 1204: ...e SPIFLG PARERRFLG is set 0 No interrupt asserted upon parity error 1 Enables an interrupt on a parity error 1 TIMEOUTENA Enables interrupt on SPIx_ENA signal time out An interrupt is to be generated when SPIFLG TIMEOUTFLG is set 0 No interrupt asserted upon SPIx_ENA signal time out 1 Enables an interrupt on a time out of the SPIx_ENA signal 0 DLENERRENA Data length error interrupt enable A data l...

Page 1205: ...erved 1 Receive interrupt is mapped to interrupt line INT1 7 Reserved 0 Reads return zero and writes have no effect 6 OVRNINTLVL Receive overrun interrupt level The overrun interrupt is not useful if receive data is serviced with CPU interrupts because the overrun and receive events share a common level interrupt signal 0 Reserved 1 Receive overrun interrupt is mapped to interrupt line INT1 5 Rese...

Page 1206: ...C1 register when there is a receive buffer full interrupt Writing a 1 to this bit Writing a 0 to SPIGCR1 ENABLE System reset 0 No new received data pending Receive buffer is empty 1 A newly received data is ready to be read Receive buffer is full Note Clearing RXINTFLG bit by writing a 1 before reading the SPIBUF sets the RXEMPTY bit of the SPIBUF register too This way one can ignore a received da...

Page 1207: ...f this error under some circumstances it is possible for a desynchronized error detected for the previous buffer to be visible in the current buffer This is due to the fact that receive completion flag interrupt will be generated when the buffer transfer is completed But decence will be detected after the buffer transfer is completed So if CPU DMA reads the received data quickly when an receive in...

Page 1208: ...rpose I O pin or as a SPI functional pin 0 SPIx_SOMI pin is a GPIO pin 1 SPIx_SOMI pin is a SPI functional pin 10 SIMOFUN Slave in master out pin function This bit determines whether the SPIx_SIMO pin is to be used as a general purpose I O pin or as a SPI functional pin 0 SPIx_SIMO pin is a GPIO pin 1 SPIx_SIMO pin is a SPI functional pin 9 CLKFUN SPI clock pin function This bit determines whether...

Page 1209: ...Controls the direction of the SPIx_SIMO pin when it is used as a general purpose I O pin If the SPIx_SIMO pin is used as a SPI functional pin the I O direction is determined by whether the SPI is configured as master or slave 0 SPIx_SIMO pin is an input 1 SPIx_SIMO pin is an output 9 CLKDIR SPIx_CLK pin direction Controls the direction of the SPIx_CLK pin when it is used as a general purpose I O p...

Page 1210: ...and writes have no effect 11 SOMIDIN SPIx_SOMI data in This bit reflects the value of the SPIx_SOMI pin 0 Current value of SPIx_SOMI pin is logic 0 1 Current value of SPIx_SOMI pin is logic 1 10 SIMODIN SPIx_SIMO data in This bit reflects the value of the SPIx_SIMO pin 0 Current value of SPIx_SIMO pin is logic 0 1 Current value of SPIx_SIMO pin is logic 1 9 CLKDIN Clock data in This bit reflects t...

Page 1211: ... 1 10 SIMODOUT SPIx_SIMO data out write This bit is only active when the SPIx_SIMO pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value of SPIx_SIMO pin is logic 0 1 Current value of SPIx_SIMO pin is logic 1 9 CLKDOUT SPIx_CLK data out write This bit is only active when the SPIx_CLK pin is configure...

Page 1212: ... output pin Reads return the value of the SPIx_SOMI pin Write 0 No effect Write 1 SPIPC3 SOMIDOUT is set to 1 10 SIMOSET SPIx_SIMO data out set This bit is only active when the SPIx_SIMO pin is configured as a general purpose output pin Reads return the value of the SPIx_SIMO pin Write 0 No effect Write 1 SPIPC3 SIMODOUT is set to 1 9 CLKSET SPIx_CLK data out set This bit is only active when the S...

Page 1213: ...eads return the value of the SPIx_SOMI pin Write 0 No effect Write 1 SPIPC3 SOMIDOUT is cleared to 0 10 SIMOCLR SPIx_SIMO data out clear This bit is only active when the SPIx_SIMO pin is configured as a general purpose output pin Reads return the value of the SPIx_SIMO pin Write 0 No effect Write 1 SPIPC3 SIMODOUT is cleared to 0 9 CLKCLR SPIx_CLK data out clear This bit is only active when the SP...

Page 1214: ...Field Value Description 31 16 Reserved 0 Reads return zero and writes have no effect 15 0 TXDATA 0 FFFFh SPI transmit data When written these bits will be copied to the shift register if it is empty If the shift register is not empty the TXBUF will hold the written values SPIGCR1 ENABLE must be set to 1 before this register can be written to Writing a 0 to the SPIGCR1 ENABLE forces the TXDATA fiel...

Page 1215: ...at the end of the current transaction The WDEL bit is supported in master mode only In slave mode this bit is ignored 0 No delay will be inserted However SPIx_SCS n pin will still be deactivated for at least 2 SPI module clock cycles if CSHOLD 0 1 After a transaction SPIFMTn WDELAY of the selected data format will be loaded into the delay counter No transaction will be performed until the SPIFMTn ...

Page 1216: ...is flag gets set to 1 under following conditions Reading the RXDATA field of the SPIBUF register Writing 1 to clear the RXINTFLG bit in the SPIFLG register 0 New data has been received and copied into the SPIBUF register 1 No data received since last reading of the SPIBUF register Write Clearing the SPIFLG RXINTFLG bit before reading the SPIBUF register indicates the received data is being ignored...

Page 1217: ...ces it is possible for a desync error detected for the previous buffer to be visible in the current buffer This is because the receive completion flag interrupt will be generated when the buffer transfer is completed But desync will be detected after the buffer transfer is completed So if CPU DMA reads the received data quickly when an RXINT is detected then the status flag may not reflect the cor...

Page 1218: ...scribed in Table 27 23 Figure 27 32 SPI Emulation Register SPIEMU 31 16 Reserved R 0 15 0 RXDATA R 0 LEGEND R Read only n value after reset Table 27 23 SPI Emulation Register SPIEMU Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return zero and writes have no effect 15 0 RXDATA 0 FFFFh SPI receive data SPI emulation is a mirror of the SPIBUF register The only difference betw...

Page 1219: ...ditional 0 5 SPIx_CLK period delay This delay is as per the SPI protocol 23 16 T2CDELAY 0 FFh Transmit end to chip select inactive delay T2CDELAY is used in master mode only It defines a hold time for the slave device that delays the chip select deactivation by a multiple of SPI module clock cycles after the last bit is transferred T2CDELAY can be configured between 2 and 256 SPI module clock cycl...

Page 1220: ... SPI detects a deassertion of the SPIx_ENA pin even before the end of the transmission See Figure 27 36 The time out value is calculated as follows tT2EDELAY T2EDELAY SPIclock Example SPIclock 8 Mbit s T2EDELAY 10h tT2EDELAY 2 μs The slave device has to disable the SPIx_ENA signal within 2 μs otherwise the DESYNC flag in SPIFLG is set and an interrupt is asserted if enabled 7 0 C2EDELAY 0 FFh Chip...

Page 1221: ... com Registers 1221 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 27 35 Example tT2CDELAY 4 SPI Module Clock Cycles Figure 27 36 Transmit Data Finished to SPIx_ENA Inactive Timeout Figure 27 37 Chip Select Active to SPIx_ENA Signal Active Timeout ...

Page 1222: ... value after reset Table 27 25 SPI Default Chip Select Register SPIDEF Field Descriptions Bit Field Value Description 31 1 Reserved 7Fh Reserved 0 CSDEF Chip select default pattern The CSDEF bit defines the state of the the SPIx_SCS 0 pin when no transmissions are performed The value of the CSDEF bit is driven directly on the SPIx_SCS 0 pin The state of the chip select pin during a transmission is...

Page 1223: ...smit data stream At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag If the parity bits do not match the PARERR flag is set in the corresponding control field The parity type even or odd can be selected via the PARPOL bit 21 WAITENA The master waits for SPIx_ENA signal from slave WAITENA is considered in master mode only In slave m...

Page 1224: ...econd inverse clock edge 1 SPI clock signal is delayed by a half SPI clock cycle versus the transmit receive data stream The first transmit bit has to output prior to the first clock edge The master and slave receive the first bit with the first edge 15 8 PRESCALE 2h FFh SPI prescaler It determines the bit transfer rate if the SPI is the network master and is directly derived from the SPI module c...

Page 1225: ...The INTVECT1 field just reflects the status of SPIFLG in a vectorized format So any updates to SPIFLG will automatically reflect in the vector value in this register Vectors for each of these interrupts will be reflected on the INTVECT1 bits when they occur Reading the vectors for the receive buffer overrun and receive buffer full interrupts will automatically clear the respective flags in the SPI...

Page 1226: ... 64 Bit Timer Plus Chapter 28 SPRUH91D March 2013 Revised September 2016 64 Bit Timer Plus This chapter describes the operation of the software programmable 64 bit Timer Plus See your device specific data manual to determine how many Timer modules are available on your device Topic Page 28 1 Introduction 1227 28 2 Registers 1245 ...

Page 1227: ...y mechanism for the device in the event of a fault condition such as a non exiting code loop 28 1 2 Features The 64 bit timer consists of the following features some features may not be supported on all timer instantiations see your device specific data manual for supported features 64 bit count up counter Timer modes 64 bit general purpose timer mode Dual 32 bit unchained general purpose timer mo...

Page 1228: ...ard Compatibility Statement This peripheral is not intended to conform to any specific industry standard Architecture 28 1 5 Architecture General Purpose Timer Mode This section describes the timer in the general purpose GP timer mode 28 1 5 1 Backward Compatible Mode The Timer Plus supports the following additional features over the other timers External clock event input Period reload External e...

Page 1229: ...clock cycles For details on the generation of the on chip clocks see the Phase Locked Loop Controller PLLC chapter The CLKSRC12 parameter in the timer control register TCR determines whether an internal or external clock is used as the clock source for the timer If the timer is configured in 64 bit mode or 32 bit chained mode CLKSRC12 controls the clock source for the entire timer If the timer is ...

Page 1230: ... 5 4 Timer Modes The following section describes the general purpose GP timer modes 28 1 5 4 1 64 Bit Timer Mode The timer can be configured as a 64 bit timer by clearing the TIMMODE bit in the timer global control register TGCR to 0 At reset 0 is the default setting for the TIMMODE bit In this mode the timer operates as a single 64 bit up counter Figure 28 3 The counter registers TIM12 and TIM34 ...

Page 1231: ...o disable the 64 bit timer out of reset 1h 1h 0 To enable the 64 bit timer for one time operation 1h 1h 1h To enable the 64 bit timer for continuous operation 1h 1h 2h To enable the 64 bit timer for continuous operation with period reload 1h 1h 3h Once the timer stops if an external clock is used as the timer clock the timer must remain disabled for at least one external clock period or the timer ...

Page 1232: ...ale counter register and one period register PRD34 to form a 32 bit prescale period register When the timer is enabled the prescale counter starts incrementing by 1 at every timer input clock cycle One cycle after the prescale counter matches the prescale period a clock signal is generated and the prescale counter register is reset to 0 see the example in Figure 28 5 The other 32 bit timer timer 1...

Page 1233: ...uality comparator PRD12 TIM34 PRD34 Input clock 32 bit prescaler Timer 3 4 Pulse generator CLKSRC12 Timer interrupt TINT12 to CPU interrupt controller Timer event TEVT12 to DMA controller 0 1 Reload period PRD34 Output event to TM64P_OUT12 32 bit timer Timer 1 2 Reload period REL12 www ti com Introduction 1233 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 ...

Page 1234: ...counting again Table 28 3 shows the bit values in TGCR to configure the 32 bit timer in chained mode Table 28 3 32 Bit Timer Chained Mode Configurations 32 Bit Timer Configuration TGCR Bit TCR Bit TIM12RS TIM34RS ENAMODE12 To place the 32 bit timer chained mode in reset 0 0 0 To disable the 32 bit timer chained mode out of reset 1h 1h 0 To enable the 32 bit timer chained mode for one time operatio...

Page 1235: ...truments Incorporated 64 Bit Timer Plus 28 1 5 4 2 2 Unchained Mode The general purpose timers can be configured as a dual 32 bit unchained timers by setting the TIMMODE bit to 1 in TGCR In the unchained mode Figure 28 6 the timer operates as two independent 32 bit timers One 32 bit timer timer 3 4 operates as a 32 bit timer being clocked by a 4 bit prescaler The other 32 bit timer timer 1 2 opera...

Page 1236: ...m the 4 bit prescaler see the example in Figure 28 7 The timer counter increments by 1 at every prescaler output clock cycle When the timer counter matches the period a maskable timer interrupt TINT34 and a timer DMA event TEVT34 are generated When the timer is configured in continuous mode the timer counter is reset to 0 on the cycle after the timer counter reaches the timer period The timer can ...

Page 1237: ...g again Table 28 4 shows the bit values in TGCR to configure the 32 bit timer in unchained mode Once the timer stops if an external clock is used as the timer clock the timer must remain disabled for at least one external clock period or the timer will not start counting again When using the external clock the count value is synchronized to the internal clock Note that when both the timer counter ...

Page 1238: ...the timer cycle is restarted when an external input event occurs on pin TM64P_IN12 In particular when an external input event occurs the timer stops counting generates output events TINT12 TEVT12 and TM64P_OUT12 copies values from the timer counter register TIM12 to the timer capture register CAP12 reloads the timer period register PRD12 if in continuous mode with period reload ENAMODE 3h and then...

Page 1239: ...4 bit general purpose TIM34 TIM12 PRD34 PRD12 Dual 32 bit chained Prescaler Timer 3 4 TIM34 PRD34 Timer Timer 1 2 TIM12 PRD12 Dual 32 bit unchained Timer Timer 1 2 TIM12 PRD12 Timer with prescaler Timer 3 4 TDDR34 bits and TIM34 PSC34 bits and PRD34 28 1 5 5 Timer Operation Boundary Conditions The following boundary conditions affect the timer operation 28 1 5 5 1 Timer Counter Overflow Timer coun...

Page 1240: ...his periodic servicing the timer counter increments until it matches the timer period and causes a watchdog timeout event When the timeout event occurs the watchdog timer resets the entire processor 28 1 6 2 Watchdog Timer Mode Restrictions The watchdog timer mode has the following restrictions No external clock source No one time enabling 28 1 6 3 Watchdog Timer Mode Operation The watchdog timer ...

Page 1241: ...ounts up waiting for DA7Eh A5C6h to WDKEY DA7Eh to WDKEY counter cleared Time out WDFLAG set WDTINT triggered Other than DA7Eh or A5C6h to WDKEY WDFLAG set WDTINT triggered A5C6h to WDKEY Disabled state Internal clock Input clock 64 bit timer counter 64 bit tmer period Equality comparator TIM34 PRD34 TIM12 PRD12 Watchdog logic and pulse generator CLKSRC12 0 WDEN WDKEY Device level reset www ti com...

Page 1242: ...ns The timer has two reset sources hardware reset and the timer reset TIM12RS and TIM34RS bits in the timer global control register TGCR 28 1 7 1 Software Reset Considerations When the TIM12RS bit in TGCR is cleared to 0 the TIM12 register is held with the current value When the TIM34RS bit in TGCR is cleared to 0 the TIM34 register is held with the current value 28 1 7 2 Hardware Reset Considerat...

Page 1243: ... value specified in the period registers TSTAT12 drives the TM64P_OUT12 pin Table 28 6 gives equations for various TSTAT12 timing parameters in pulse and clock modes The output mode is selected with the clock pulse bit CPn in the timer control register TCR In pulse mode the PWID12 bit in TCR sets the pulse width between 1 to 4 timer clock periods The TM64P_OUT12 pin may be inverted using the INVOU...

Page 1244: ...he timer period registers set the period compare interrupt enable bit PRDINTENn in the interrupt control and status register INTCTLSTAT The event status for this case is reflected in the period compare interrupt status bit PRDINTSTATn which is also in INTCTLSTAT The PRDINTSTATn bit is cleared by writing a 1 to the bit Similarly to generate events in Event Capture Mode set the event interrupt enabl...

Page 1245: ...e Register Section 28 2 3 Ch GPDATGPDIR GPIO Data and GPIO Direction Register Section 28 2 4 10h TIM12 Timer Counter Register 12 Section 28 2 5 14h TIM34 Timer Counter Register 34 Section 28 2 5 18h PRD12 Timer Period Register 12 Section 28 2 6 1Ch PRD34 Timer Period Register 34 Section 28 2 6 20h TCR Timer Control Register Section 28 2 7 24h TGCR Timer Global Control Register Section 28 2 8 28h W...

Page 1246: ...September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated 64 Bit Timer Plus Table 28 8 Timer Registers continued Offset Acronym Register Description Section 7Ch CMP7 Compare Register 7 Timer Compare Registers CMP0 CMP7 ...

Page 1247: ...ister EMUMGT is shown in Figure 28 14 and described in Table 28 10 Figure 28 14 Emulation Management Register EMUMGT 31 16 Reserved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 28 10 Emulation Management Register EMUMGT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 SOFT Determines emulation mode functionalit...

Page 1248: ... 0 TM64P_OUT12 is used as a TIMER output pin 1 TM64P_OUT12 is used as a GPIO pin 16 GPENI12 Enable TM64P_IN12 to function in GPIO mode 0 TM64P_IN12 is used as a TIMER input pin 1 TM64P_IN12 is used as a GPIO pin 15 6 Reserved 0 Reserved 5 GPINT12INVO Invert interrupt event signal from TM64P_OUT12 when GPINT12ENO 1 0 Rising signal edge on TM64P_OUT12 generates the interrupt event 1 Falling signal e...

Page 1249: ...T12 functions as an input pin in GPIO mode 1 TM64P_OUT12 functions as an output pin in GPIO mode TM64P_OUT12 cannot capture GPIO interrupt events when configured as output 16 GPDIRI12 Select direction of TM64P_IN12 in GPIO mode 0 TM64P_IN12 functions as an input pin in GPIO mode 1 TM64P_IN12 functions as an output pin in GPIO mode TM64P_IN12 cannot capture GPIO interrupt events when configured as ...

Page 1250: ... TIM12 is shown in Figure 28 17 and described in Table 28 13 Figure 28 17 Timer Counter Register 12 TIM12 31 0 TIM12 R W 0 LEGEND R W Read Write R Read only n value after reset Table 28 13 Timer Counter Register 12 TIM12 Field Descriptions Bit Field Value Description 31 0 TIM12 0 FFFF FFFFh TIM12 count bits This 32 bit value is the current count of the main counter 28 2 5 2 Timer Counter Register ...

Page 1251: ...register 12 PRD12 is shown in Figure 28 19 and described in Table 28 15 Figure 28 19 Timer Period Register 12 PRD12 31 0 PRD12 R W 0 LEGEND R W Read Write R Read only n value after reset Table 28 15 Timer Period Register PRD12 Field Descriptions Bit Field Value Description 31 0 PRD12 0 FFFF FFFFh PRD12 period bits This 32 bit value is the number of timer input clock cycles to count 28 2 6 2 Timer ...

Page 1252: ...ins current value 1h The timer is enabled one time The timer stops after the counter reaches the period 2h The timer is enabled continuously TIM34 increments until the timer counter matches the period resets the timer counter to 0 on the cycle after matching and continues 3h The timer is enabled continuously with period reload TIMn increments until the timer counter matches the period resets the t...

Page 1253: ...the cycle after matching reloads the period register with the values in the reload registers RELn and continues counting 5 4 PWID12 0 3h Pulse width Determines the pulse width on the TSTAT12 bit and the TM64P_OUT12 pin when the clock pulse mode is set to pulse 0 TSTAT12 stays active for one timer clock cycle when the timer counter reaches the period 1h TSTAT12 stays active for two timer clock cycl...

Page 1254: ...cycle after matching PRD34 and timer 3 4 continues if timer 3 4 is enabled continuously 11 8 PSC34 0 Fh TIM34 pre scalar counter specifies the count for timer 3 4 7 5 Reserved 0 Reserved 4 PLUSEN Enable new timer plus features 0 Enable backward compatibility New timer features are unavailable 1 Disable backward compatibility New timer features are available 3 2 TIMMODE 0 3h TIMMODE determines the ...

Page 1255: ...ad only n value after reset Table 28 19 Watchdog Timer Control Register WDTCR Field Descriptions Bit Field Value Description 31 16 WDKEY 0 FFFFh 16 bit watchdog timer service key Only the sequence of an A5C6h followed by a DA7Eh services the watchdog Not applicable in regular timer mode 15 WDFLAG Watchdog flag bit WDFLAG can be cleared by enabling the watchdog timer by device reset or being writte...

Page 1256: ...GEND R W Read Write R Read only n value after reset Table 28 20 Timer Reload Register 12 REL12 Field Descriptions Bit Field Value Description 31 0 REL12 0 FFFF FFFFh Period reload bits 28 2 11 Timer Reload Register 34 REL34 The timer reload register 34 REL34 is shown in Figure 28 25 and described in Table 28 21 Figure 28 25 Timer Reload Register 34 REL34 31 0 REL34 R W 0 LEGEND R W Read Write R Re...

Page 1257: ...ead Write R Read only n value after reset Table 28 22 Timer Capture Register 12 CAP12 Field Descriptions Bit Field Value Description 31 0 CAP12 0 FFFF FFFFh Captured timer counter bits 28 2 13 Timer Capture Register 34 CAP34 The timer capture register 34 CAP34 is shown in Figure 28 27 and described in Table 28 23 Figure 28 27 Timer Capture Register 34 CAP34 31 0 CAP34 R W 0 LEGEND R W Read Write R...

Page 1258: ...clear this bit 0 Interrupt has not occurred 1 Interrupt has occurred 18 EVTINTEN34 Enables the interrupt generation when timer is in capture mode 0 Disable interrupt when in event capture mode 1 Enable interrupt when in event capture mode 17 PRDINTSTAT34 Interrupt status which reflects the condition that timer counter matched the period register when timer is enabled Write a 1 to clear this bit 0 ...

Page 1259: ...imer Compare Registers CMP0 CMP7 The timer compare register CMPn is shown in Figure 28 29 and described in Table 28 25 Figure 28 29 Timer Compare Register CMPn 31 0 CMPn R W 0 LEGEND R W Read Write n value after reset Table 28 25 Timer Compare Register CMPn Field Descriptions Bit Field Value Description 31 0 CMPn 0 FFFF FFFFh Timer compare register When PLUSEN 1 in the timer global control registe...

Page 1260: ...ART Chapter 29 SPRUH91D March 2013 Revised September 2016 Universal Asynchronous Receiver Transmitter UART This chapter describes the universal asynchronous receiver transmitter UART peripheral See your device specific data manual to determine how many UARTs are available on your device Topic Page 29 1 Introduction 1261 29 2 Peripheral Architecture 1263 29 3 Registers 1274 ...

Page 1261: ...rallel to serial conversion on data received from the CPU The CPU can read the UART status at any time The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link The UART includes a programmable baud generator capable of dividing the UART input clock by divisors from 1 to 65535 and producing a 16 reference c...

Page 1262: ...pheral Bus S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Control Logic 16 8 8 8 8 8 Interrupt to CPU 16 8 pin pin 8 8 8 8 Power and Emulation Control Register Event to DMA controller Introduction www ti com 1262 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments I...

Page 1263: ...s 16 BCLK cycles or thirteen times 13 the baud rate each received or transmitted bit lasts 13 BCLK cycles When the UART is receiving the bit is sampled in the 8th BCLK cycle for 16 over sampling mode and on the 6th BCLK cycle for 13 over sampling mode The 16 or 13 reference clock is selected by configuring the OSM_SEL bit in the mode definition register MDR The formula to calculate the divisor is ...

Page 1264: ...ships Between Data Bit BCLK and UART Input Clock Table 29 1 Baud Rate Examples for 150 MHZ UART Input Clock and 16 Over sampling Mode Baud Rate Divisor Value Actual Baud Rate Error 2400 3906 2400 154 0 01 4800 1953 4800 372 0 01 9600 977 9595 701 0 04 19200 488 19211 066 0 06 38400 244 38422 131 0 06 56000 167 56137 725 0 25 128000 73 129807 7 0 33 3000000 3 3125000 4 00 Table 29 2 Baud Rate Examp...

Page 1265: ...of peripheral functions in the smallest possible package Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings See your device specific data manual to determine how pin multiplexing affects the UART 29 2 4 Protocol Description 29 2 4 1 Transmission The UART transmitter section includes a transmitter hold register TH...

Page 1266: ...on the STOP bit selection The UART receives in the following format 1 START bit data bits 5 6 7 8 1 PARITY bit optional 1 STOP bit It receives 1 START bit 5 6 7 or 8 data bits depending on the data width selection 1 PARITY bit if parity is selected and 1 STOP bit The protocol formats are shown in Figure 29 4 Figure 29 4 UART Protocol Formats Transmit Receive for 5 bit data parity Enable 1 STOP bit...

Page 1267: ...hen the transmitter FIFO is empty and it is cleared when at least one byte is loaded into the FIFO or IIR is read 29 2 5 2 Reception The UART receiver section includes a receiver shift register RSR and a receiver buffer register RBR When the UART is in the FIFO mode RBR is a 16 byte FIFO Timing is supplied by the 16 receiver clock Receiver section control is a function of the UART line control reg...

Page 1268: ...et when a character is transferred from the receiver shift register RSR to the empty receiver FIFO The DR bit remains set until the FIFO is empty again A receiver time out interrupt occurs if all of the following conditions exist At least one character is in the FIFO The most recent character was received more than four continuous character times ago A character time is the time allotted for 1 STA...

Page 1269: ...itter holding register THR and the transmitter shift register TSR are empty The THRE bit indicates when THR is empty The BI break FE framing error PE parity error and OE overrun error bits specify which error or errors have occurred The DR data ready bit is set as long as there is at least one byte in the receiver FIFO Also in the FIFO poll mode The interrupt identification register IIR is not aff...

Page 1270: ... where an additional byte is sent 29 2 5 4 2 UARTn_CTS Behavior The transmitter checks UARTn_CTS before sending the next data byte If UARTn_CTS is active the transmitter sends the next byte To stop the transmitter from sending the following byte UARTn_CTS must be released before the middle of the last STOP bit that is currently being sent see Figure 29 7 When flow control is enabled UARTn_CTS leve...

Page 1271: ...LL and DLH 3 If the FIFOs will be used select the desired trigger level and enable the FIFOs by writing the appropriate values to the FIFO control register FCR The FIFOEN bit in FCR must be set first before the other bits in FCR are configured 4 Choose the desired protocol settings by writing the appropriate values to the line control register LCR 5 If autoflow control is desired write appropriate...

Page 1272: ...o using RDAINT the CPU can poll the DR bit in the line status register LSR In the FIFO mode this is not a functionally equivalent alternative because the DR bit does not respond to the FIFO trigger level The DR bit only indicates the presence or absence of unread characters RTOINT Receiver time out condition in the FIFO mode only No characters have been removed from or input to the receiver FIFO d...

Page 1273: ...Power and Sleep Controller PSC The PSC acts as a master controller for power management for all of the peripherals on the device For detailed information on power management procedures using the PSC see the Power and Sleep Controller PSC chapter 29 2 11 Emulation Considerations The FREE bit in the power and emulation management register PWREMU_MGMT determines how the UART responds to an emulation ...

Page 1274: ...ify DLH DLH can also be accessed with address offset 24h IIR and FCR share one address Regardless of the value of the DLAB bit reading from the address gives the content of IIR and writing modifies FCR Table 29 6 UART Registers Offset Acronym Register Description Section 0h RBR Receiver Buffer Register read only Section 29 3 1 0h THR Transmitter Holding Register write only Section 29 3 2 4h IER In...

Page 1275: ...aced in RBR and the receiver data ready interrupt is enabled DR 1 in IER an interrupt is generated This interrupt is cleared when the character is read from RBR In the FIFO mode the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register FCR and it is cleared when the FIFO contents drop below the trigger level Access considerations RBR THR and DLL ...

Page 1276: ...nabled ETBEI 1 in IER an interrupt is generated This interrupt is cleared when a character is loaded into THR or the interrupt identification register IIR is read In the FIFO mode the interrupt is generated when the transmitter FIFO is empty and it is cleared when at least one byte is loaded into the FIFO or IIR is read Access considerations RBR THR and DLL share one address To load THR write 0 to...

Page 1277: ...t IER is always selected at the shared address Figure 29 11 Interrupt Enable Register IER 31 16 Reserved R 0 15 4 3 2 1 0 Reserved Rsvd ELSI ETBEI ERBI R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 29 9 Interrupt Enable Register IER Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 EDSSI 0 Enable Modem Status Interrupt 2 ELSI Receiv...

Page 1278: ...etermine whether the UART is in the FIFO mode or the non FIFO mode Access consideration IIR and FCR share one address Regardless of the value of the DLAB bit in LCR reading from the address gives the content of IIR and writing to the address modifies FCR Figure 29 12 Interrupt Identification Register IIR 31 16 Reserved R 0 15 8 7 6 5 4 3 1 0 Reserved FIFOEN Reserved INTID IPEND R 0 R 0 R 0 R 0 R 1...

Page 1279: ...from or input to the receiver FIFO during the last four character times see Table 29 4 and there is at least one character in the receiver FIFO during this time One of the following events A character is read from the receiver FIFO 1 A new character arrives in the receiver FIFO The URRST bit in the power and emulation management register PWREMU_MGMT is loaded with 0 3 0 0 1 0 Transmitter holding r...

Page 1280: ...d if the interrupt request is enabled Once the FIFO drops below the trigger level the interrupt is cleared 0 1 byte 1h 4 bytes 2h 8 bytes 3h 14 bytes 5 4 Reserved 0 Reserved 3 DMAMODE1 DMA MODE1 enable if FIFOs are enabled Always write 1 to DMAMODE1 After a hardware reset change DMAMODE1 from 0 to 1 DMAMOD1 1 is a requirement for proper communication between the UART and the EDMA controller 0 DMA ...

Page 1281: ...ed by IER and DLH the CPU can read from and write to IER 1 Allows access to the divisor latches of the baud generator during a read or write operation DLL and DLH At the address shared by RBR THR and DLL the CPU can read from and write to DLL At the address shared by IER and DLH the CPU can read from and write to DLH 6 BC Break control 0 Break condition is disabled 1 Break condition is transmitted...

Page 1282: ...e generated When WLS 1h 2h or 3h 2 STOP bits are generated 1 0 WLS 0 3h Word length select Number of bits in each transmitted or received serial character When STB 1 the WLS bit determines the number of STOP bits 0 5 bits 1h 6 bits 2h 7 bits 3h 8 bits Table 29 14 Relationship Between ST EPS and PEN Bits in LCR ST Bit EPS Bit PEN Bit Parity Option x x 0 Parity disabled No PARITY bit is transmitted ...

Page 1283: ...gnals to provide handshaking between UARTs during data transfer When AFE 1 the RTS bit determines the autoflow control enabled Note that all UARTs do not support this feature see your device specific data manual for supported features If this feature is not available this bit is reserved and should be cleared to 0 0 Autoflow control is disabled 1 Autoflow control is enabled When RTS 0 UARTn_CTS is...

Page 1284: ...XFIFOE was cleared because the CPU read the erroneous character from the receiver FIFO and there are no more errors in the receiver FIFO 1 At least one parity error framing error or break indicator in the receiver FIFO 6 TEMT Transmitter empty TEMT indicator In non FIFO mode 0 Either the transmitter holding register THR or the transmitter shift register TSR contains a data character 1 Both the tra...

Page 1285: ...cleared because the CPU read the erroneous data from the receiver FIFO and the next character to be read from the FIFO has no framing error 1 A framing error has been detected with the character at the top of the receiver FIFO 2 PE Parity error PE indicator A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control regist...

Page 1286: ... is generated In non FIFO mode 0 Data is not ready or the DR bit was cleared because the character was read from the receiver buffer register RBR 1 Data is ready A complete incoming character has been received and transferred into the receiver buffer register RBR In FIFO mode 0 Data is not ready or the DR bit was cleared because all of the characters in the receiver FIFO have been read 1 Data is r...

Page 1287: ...SR 0 Complement of the Data Set Ready input When the UART is in the diagnostic test mode loopback mode MCR 4 1 this bit is equal to the MCR bit 0 DTR 4 CTS 0 Complement of the Clear To Send input When the UART is in the diagnostic test mode loopback mode MCR 4 1 this bit is equal to the MCR bit 1 RTS 3 DCD 0 Change in DCD indicator bit DCD indicates that the DCD input has changed state since the l...

Page 1288: ... baud clock in the baud generator The latches are in DLH and DLL DLH holds the most significant bits of the divisor and DLL holds the least significant bits of the divisor These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator Writing to the divisor latches results in two wait states being inserted during the write access w...

Page 1289: ...ield Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 DLL 0 FFh The 8 least significant bits LSBs of the 16 bit divisor for generation of the baud clock in the baud rate generator Figure 29 20 Divisor MSB Latch DLH 31 16 Reserved R 0 15 8 7 0 Reserved DLH R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 29 21 Divisor MSB Latch DLH Field Descriptions Bit Fi...

Page 1290: ... shown in Figure 29 22 and described in Table 29 23 Figure 29 21 Revision Identification Register 1 REVID1 31 0 REVID1 R 1102 0002h LEGEND R Read only n value after reset Table 29 22 Revision Identification Register 1 REVID1 Field Descriptions Bit Field Value Description 31 0 REVID1 1102 0002h Peripheral Identification Number Figure 29 22 Revision Identification Register 2 REVID2 31 16 Reserved R ...

Page 1291: ...ons Bit Field Value Description 31 16 Reserved 0 Reserved 15 Reserved 0 Reserved This bit must always be written with a 0 14 UTRST UART transmitter reset Resets and enables the transmitter 0 Transmitter is disabled and in reset state 1 Transmitter is enabled 13 URRST UART receiver reset Resets and enables the receiver 0 Receiver is disabled and in reset state 1 Receiver is enabled 12 1 Reserved 1 ...

Page 1292: ...n register MDR determines the over sampling mode for the UART MDR is shown in Figure 29 24 and described in Table 29 25 Figure 29 24 Mode Definition Register MDR 31 16 Reserved R 0 15 1 0 Reserved OSM_SEL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 29 25 Mode Definition Register MDR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 OSM_SEL Over Sam...

Page 1293: ...nstruments Incorporated Universal Serial Bus OHCI Host Controller Chapter 30 SPRUH91D March 2013 Revised September 2016 Universal Serial Bus OHCI Host Controller This chapter describes the universal serial bus OHCI host controller Topic Page 30 1 Introduction 1294 30 2 Architecture 1295 30 3 Registers 1299 ...

Page 1294: ...re already familiar with the USB Specification and OHCI Specification for USB The USB1 1 host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB These registers and data structures are the mechanisms by which a USB host controller driver software package can control the USB1 1 host controller The OHCI Specification for USB a...

Page 1295: ... of the device level power sleep controller 1 PSC1 module This module controls many local power sleep controller modules and local power sleep controller 2 LPSC2 of PSC1 controls the USB1 1 OHCI host controller 30 2 1 3 48 MHz Reference Clock This device includes an integrated USB 1 1 Phy for the OHCI Host Controller s Root Hub Port 0 This Phy requires a 48 MHz reference clock for proper operation...

Page 1296: ...scussions of USB requirements and OHCI controller operation 30 2 3 Differences From OHCI Specification for USB The USB1 1 module OHCI compatible host controller implementation does not implement every aspect of the functionality defined in the OHCI Specification for USB The differences focus on power switching overcurrent reporting and the OHCI ownership change interrupt Other restrictions are imp...

Page 1297: ...RSMRCY after a bus segment transitions from resume signaling to normal operational mode During that time only start of frame packets are to be sent on the bus segment The system software should disable all list enable bits HCCONTROL PLE HCCONTROL IE HCCONTROL CLE and HCCONTROL BLE and then wait for at least 1 ms before setting the host controller into USB suspend state via HCCONTROL HCFS When rest...

Page 1298: ...fabric allows the USB1 1 host controller to access system memory 30 2 7 Physical Addressing Transactions on the internal bus use physical addresses so all system memory accesses initiated by the USB1 1 host controller must use physical addresses The CPU can be configured to use virtual addressing In this case software manipulates virtual addresses that may or may not be identical to physical addre...

Page 1299: ... 01E2 5004h HCCONTROL HC Operating Mode Register Section 30 3 2 01E2 5008h HCCOMMANDSTATUS HC Command and Status Register Section 30 3 3 01E2 500Ch HCINTERRUPTSTATUS HC Interrupt and Status Register Section 30 3 4 01E2 5010h HCINTERRUPTENABLE HC Interrupt Enable Register Section 30 3 5 01E2 5014h HCINTERRUPTDISABLE HC Interrupt Disable Register Section 30 3 6 01E2 5018h HCHCCA HC HCAA Address Regi...

Page 1300: ... R Read only n value after reset Table 30 2 OHCI Revision Number Register HCREVISION Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 REV 10h OHCI revision number 30 3 2 HC Operating Mode Register HCCONTROL The HC operating mode register HCCONTROL controls the operating mode of the USB1 1 host controller HCCONTROL is shown in Figure 30 3 and described in Table 30 3 Figur...

Page 1301: ...a current ED before it reenables the bulk list 1 Enables processing of the bulk ED list The HC head bulk register HCBULKHEADED must be 0 or point to a valid ED before setting this bit The HC current bulk register HCBULKCURRENTED must be 0 or point to a valid ED before setting this bit 4 CLE Control list enable 0 The control ED list is not processed in the next 1 ms frame The host controller driver...

Page 1302: ...iver sets this bit to gain ownership of the host controller The processor does not support SMI interrupts so no ownership change interrupt occurs 2 BLF 0 1 Bulk list filled The host controller driver must set this bit if it modifies the bulk list to include new TDs If the HC current bulk register HCBULKCURRENTED is 0 the USB1 1 host controller does not begin processing bulk list EDs unless this bi...

Page 1303: ... FNO Frame number overflow A write of 1 clears this bit a write of 0 has no effect 0 A frame number overflow has not occurred 1 A frame number overflow has occurred 4 UE Unrecoverable error A write of 1 clears this bit a write of 0 has no effect 0 An unrecoverable error has not occurred 1 An unrecoverable error has occurred on the OCPI bus or that an isochronous TD PSW field condition code was not...

Page 1304: ... a write of 0 has no effect A write of 1 to the corresponding bit in the HC interrupt disable register HCINTERRUPTDISABLE clears this bit 0 Frame number overflow interrupts do not propagate 1 When MIE is 1 allows frame number overflow interrupts to propagate to the level 2 interrupt controller 4 UE Unrecoverable error A write of 1 sets this bit a write of 0 has no effect A write of 1 to the corres...

Page 1305: ... No effect 1 Clears the MIE bit in the HC interrupt enable register HCINTERRUPTENABLE 30 OC 0 1 Ownership change 29 7 Reserved 0 Reserved 6 RHSC Root hub status change Read always returns 0 0 No effect 1 Clears the RHSC bit in the HC interrupt enable register HCINTERRUPTENABLE 5 FNO Frame number overflow Read always returns 0 0 No effect 1 Clears the FNO bit in the HC interrupt enable register HCI...

Page 1306: ...Reserved 0 Reserved 30 3 8 HC Current Periodic Register HCPERIODCURRENTED The HC current periodic register HCPERIODCURRENTED defines the physical address of the next endpoint descriptor ED on the periodic ED list HCPERIODCURRENTED is shown in Figure 30 9 and described in Table 30 9 Figure 30 9 HC Current Periodic Register HCPERIODCURRENTED 31 16 PCED R 0 15 4 3 0 PCED Reserved R 0 R 0 LEGEND R Rea...

Page 1307: ...restrictions on physical addresses see Section 30 2 7 3 0 Reserved 0 Reserved 30 3 10 HC Current Control Register HCCONTROLCURRENTED The HC current control register HCCONTROLCURRENTED defines the physical address of the next endpoint descriptor ED on the control ED list HCCONTROLCURRENTED is shown in Figure 30 11 and described in Table 30 11 Figure 30 11 HC Current Control Register HCCONTROLCURREN...

Page 1308: ...e restrictions on physical addresses see Section 30 2 7 3 0 Reserved 0 Reserved 30 3 12 HC Current Bulk Register HCBULKCURRENTED The HC current bulk register HCBULKCURRENTED defines the physical address of the next endpoint descriptor ED on the bulk ED list HCBULKCURRENTED is shown in Figure 30 13 and described in Table 30 13 Figure 30 13 HC Current Bulk Register HCBULKCURRENTED 31 16 BCED R W 0 1...

Page 1309: ...Ds on the done queue This register is automatically updated by the USB1 1 host controller 3 0 Reserved 0 Reserved 30 3 14 HC Frame Interval Register HCFMINTERVAL The HC frame interval register HCFMINTERVAL defines the number of 12 MHz clock pulses in each USB frame HCFMINTERVAL is shown in Figure 30 15 and described in Table 30 15 Figure 30 15 HC Frame Interval Register HCFMINTERVAL 31 30 16 FIT F...

Page 1310: ... 0 3FFFh Frame remaining The number of full speed bit times remaining in the current frame This field is automatically reloaded with the frame interval FI value in the HC frame interval register HCFMINTERVAL at the beginning of every frame 30 3 16 HC Frame Number Register HCFMNUMBER The HC frame number register HCFMNUMBER reports the current USB frame number HCFMNUMBER is shown in Figure 30 17 and...

Page 1311: ... the first 10 of the frame then periodic EDs have priority for the remaining 90 of the frame 30 3 18 HC Low Speed Threshold Register HCLSTHRESHOLD The HC low speed threshold register HCLSTHRESHOLD defines the latest time in a frame that the USB1 1 host controller can begin a low speed packet HCLSTHRESHOLD is shown in Figure 30 19 and described in Table 30 19 Figure 30 19 HC Low Speed Threshold Reg...

Page 1312: ...elationship to the OTG controller register bits that relate to VBUS System software can update this register to simplify host controller driver and or OTG driver coding 23 13 Reserved 0 Reserved 12 NOCP 1 No overcurrent protection Because the device does not provide signals to allow connection of external overcurrent indication signals to the USB1 1 host controller this bit defaults to 1 that indi...

Page 1313: ... is the port power control mask for downstream port 2 Defines whether downstream port 2 has port power controlled by the global power control System software can update these bits to simplify host controller driver and or OTG driver coding 0 Global power control is implemented for downstream port 2 1 Per port power control is implemented for downstream port 2 17 PPCM 1 Port power control mask PPCM...

Page 1314: ...status change Because the root hub does not support the local power status feature this bit defaults to 0 and has no effect This bit has no relationship to the OTG controller register bits that relate to VBUS System software can update this register to simplify host controller driver and or OTG driver coding 15 DRWE Device remote wake up enable When 1 this bit enables a connect status change event...

Page 1315: ...pend status change A write of 1 clears this bit a write of 0 has no effect 0 Port 1 port suspend status has not changed 1 Port 1 port suspend status has changed Suspend status is considered to have changed only after the resume pulse low speed EOP and 3 ms synchronization delays have been completed 17 PESC Port 1 enable status change A write of 1 clears this bit a write of 0 has no effect 0 Port 1...

Page 1316: ... The device does not provide inputs for signaling external overcurrent indication to the USB1 1 host controller Overcurrent monitoring if required must be handled through some other mechanism 0 Port 1 port overcurrent condition has not occurred 1 Port 1 port overcurrent condition has occurred 2 PSS SPS Port 1 port suspend status set port suspend A write of 1 to this bit when port 1 current connect...

Page 1317: ... controller register bits that relate to VBUS 18 PSSC Port 2 suspend status changed A write of 1 clears this bit a write of 0 has no effect 0 Port 2 port suspend status has not changed 1 Port 2 port suspend status has changed Suspend status is considered to have changed only after the resume pulse low speed EOP and 3 ms synchronization delays have been completed 17 PESC Port 2 enable status change...

Page 1318: ...uired must be handled through some other mechanism This bit has no relationship to the OTG controller register bits that relate to VBUS 0 A write of 0 has no effect 1 A write of 1 to this bit when port 2 port suspend status is 1 causes resume signaling on port 2 A write of 1 when port 2 port suspend status is 0 has no effect 2 PSS SPS Port 2 port suspend status set port suspend When read as 1 indi...

Page 1319: ...ments Incorporated Universal Serial Bus 2 0 USB Controller Chapter 31 SPRUH91D March 2013 Revised September 2016 Universal Serial Bus 2 0 USB Controller This chapter describes the universal serial bus USB controller Topic Page 31 1 Introduction 1320 31 2 Architecture 1321 31 3 Use Cases 1388 31 4 Registers 1400 ...

Page 1320: ...for additional versatility supporting operation capability as a host or peripheral 31 1 2 Features The USB has the following features Operating as a host it complies with the USB 2 0 standard for high speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps operations with a peripheral Operating as a peripheral it complies with the USB 2 0 standard for high speed 480 Mbps and full speed 12 Mbps op...

Page 1321: ... in the chip configuration 2 register CFGCHIP2 of the System Configuration Module The USB_REFCLKIN source should be selected when it is not possible such as when specific audio rates are required to operate the device at one of the allowed input frequencies to the USB2 0 subsystem The USB2 0 subsystem peripheral bus clock is sourced from SYSCLK2 Table 31 1 determines the source origination as well...

Page 1322: ...ncies 0 1 USB_REFCLKIN USB_REFCLKIN USB_REFCLKIN must be 48 MHz The PLL inside the USB2 0 PHY can be configured to accept this input clock frequency 1 0 PLL0_AUXCLK CLK48MHz output from USB2 0 PHY PLL0_AUXCLK must be 12 24 48 19 2 38 4 13 26 20 or 40 MHz The PLL inside the USB2 0 PHY can be configured to accept any of these input clock frequencies 1 1 PLL0_AUXCLK USB_REFCLKIN PLL0_AUXCLK must be 1...

Page 1323: ...this signal for HNP and SRP For device or host only mode of operation pull up this pin to 5V For host mode of operation also pull up the USB power signal on the USB connector to 5V For mixed host device mode of operation tie this to the charge pump USB0_DRVVBUS I O Z Digital output to control external 5 V supply USB0_VDDA33 I O Z USB0 PHY 3 3V supply USB0_VDDA18 I O Z USB0 PHY 1 8V supply input US...

Page 1324: ...The final task is to turn on the PHY PLL and wait until it locks You should wait for the PHY clock good status to be set prior to ending the PHY initialization process 31 2 5 VBUS Voltage Sourcing Control When the USB controller assumes the role of a host it is required to supply 5V power to an attached device through its VBUS line In order to achieve this task the USB controller requires the use ...

Page 1325: ...o that it start sourcing the required 5V power must be 4 75V The USB2 0 controller will then wait to for the voltage of the USB0_VBUS goes high If it does not see the power on the USB0_VBUS pin greater than Vbus Valid 4 4V it will generate an interrupt to the user indicating the existence of a problem Assuming that the voltage level of the USB0_VBUS is found to be above Vbus Valid then the USB 2 0...

Page 1326: ... routine Yes interrupt Receive Host Tx routine No Yes Transmit interrupt interrupt EP0 Yes Peripheral EP0 routine No interrupt Receive No Rx routine Peripheral Yes Transmit interrupt Tx routine Peripheral Yes interrupt SOF routine Resume Yes interrupt Disconn Disconnect Yes routine Suspend interrupt Suspend Yes routine Architecture www ti com 1326 SPRUH91D March 2013 Revised September 2016 Submit ...

Page 1327: ...e controller will not then be able to detect Resume signaling on the USB As a result some external hardware will be needed to detect Resume signaling by monitoring the DM and DP signals so that the clock to the controller can be restarted Resume Signaling When resume signaling occurs on the bus first the clock to the controller must be restarted if necessary Then the controller will automatically ...

Page 1328: ...requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSR0 bit 0 will also have been set The 8 byte command should then be read from the endpoint 0 FIFO decoded and the appropriate action taken For example if the command is SET_ADDRESS the 7 bit address value contained in the command should be written to the FADDR register The PERI_CSR0 register should then be writte...

Page 1329: ...ad from the endpoint 0 FIFO If the length of the data associated with the request indicated by the wLength field in the command is greater than the maximum packet size for endpoint 0 further data packets will be sent In this case PERI_CSR0 should be written to set the SERV_RXPKTRDY bit but the DATAEND bit should not be set When all the expected data packets have been received the PERI_CSR0 registe...

Page 1330: ...software the interrupt is just a confirmation that the request completed successfully If the command is an unrecognized command or for some other reason cannot be executed then when it has been decoded the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit bit 6 and to set the SENDSTALL bit bit 5 When the host requests data the controller will send a STALL to tell the host that the ...

Page 1331: ...a Int Int phase clear RxPktRdy Unload FIFO and and set DataEnd Int OUT data phase Int IN Int RX state Idle Unload device req and clear RxPktRdy Setup Int Sequence 3 Status phase IN Int No data phase DataEnd clear RxPktRdy and set Unload device req and Idle CPU actions Idle Tx state Rx state Sequence 1 Sequence 2 Sequence 3 www ti com Architecture 1331 SPRUH91D March 2013 Revised September 2016 Sub...

Page 1332: ...ontroller receiving data from the bus The service routine must check for this by testing the RXPKTRDY bit of PERI_CSR0 bit 0 If this bit is set then the controller has received a SETUP packet This must be unloaded from the FIFO and decoded to determine the action the controller must take Depending on the command contained within the SETUP packet endpoint 0 will enter one of three states If the com...

Page 1333: ...p end Yes State Yes No IDLE IDLE mode TX mode No TX State Yes RX mode RX State Yes By default www ti com Architecture 1333 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller Figure 31 6 Service Endpoint 0 Flow Chart ...

Page 1334: ...ed September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller 31 2 7 1 1 5 1 IDLE Mode IDLE mode is the mode the endpoint 0 control must select at power on or reset and is the mode to which the endpoint 0 control should return when the RX and TX modes are terminated It is also the mode in which the SETUP phase of control ...

Page 1335: ...IN tokens See Figure 31 8 Three events can cause TX mode to be terminated before the expected amount of data has been sent 1 The host sends an invalid token causing a SETUPEND condition bit 4 of PERI_CSR0 set 2 The software sends a packet containing less than the maximum packet size for endpoint 0 3 The software sends an empty data packet Until the transaction is terminated the software simply nee...

Page 1336: ... RX mode to be terminated before the expected amount of data has been received as shown in Figure 31 9 1 The host sends an invalid token causing a SETUPEND condition setting bit 4 of PERI_CSR0 2 The host sends a packet which contains less than the maximum packet size for endpoint 0 3 The host sends an empty data packet Until the transaction is terminated the software unloads the FIFO when it recei...

Page 1337: ... this indicates that the host has sent another SETUP packet and the software should then process this command If the software wants to abort the current transfer because it cannot process the command or has some other internal error then it should set the SENDSTALL bit bit 5 of PERI_CSR0 The controller will then send a STALL packet to the host set the SENTSTALL bit bit 2 of PERI_CSR0 and generate ...

Page 1338: ... must be enabled Bit 11 FRCDATATOG Cleared to 0 to allow normal data toggle operations Bit 10 DMAMODE Set to 1 when DMA is enabled When the endpoint is first configured following a SET_CONFIGURATION or SET_INTERFACE command on Endpoint 0 the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit bit 6 This will ensure that the data toggle which is handled automatically by the control...

Page 1339: ...d the data toggle sequence should be restarted by setting the CLRDATATOG bit in the PERI_TXCSR register bit 6 31 2 7 1 2 2 Bulk OUT Transactions A Bulk OUT transaction is used to transfer non periodic data from the host to the function controller The following optional features are available for use with an Rx endpoint used in peripheral mode for Bulk OUT transactions Double packet buffering When ...

Page 1340: ...ze of the data block is a multiple of wMaxPacketSize a null data packet will be sent after the data to signify that the transfer is complete In the general case the application software will need to read each packet from the FIFO individually If large blocks of data are being transferred the overhead of calling an interrupt service routine to unload each packet can be avoided by using DMA 31 2 7 1...

Page 1341: ...nabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature allows the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_TXCSR register needs to...

Page 1342: ...enerate a SOF_PULSE when the SOF packet has been lost The interrupts may still be used to set the TXPKTRDY bit in PERI_TXCSR bit 0 and to check for data overruns underruns Starting up a double buffered Isochronous IN pipe can be a source of problems Double buffering requires that a data packet is not transmitted until the frame microframe after it is loaded There is no problem if the function load...

Page 1343: ...e PERI_RXCSR register should be set as shown in Table 31 7 Table 31 7 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Set to 1 to enable isochronous protocol Bit 13 DMAEN Set to 1 if a DMA request is required for this endpoint Bit 12 DISNYET Ignored in isochronous transfers Bit 11 DMAMODE Always clear this bit to 0 31 2 7 ...

Page 1344: ...then exit Suspend mode and automatically set the RESUME bit in the POWER register bit 2 to take over generating the Resume signaling from the target If the Resume interrupt is enabled an interrupt will be generated Reset Signaling If the RESET bit in the POWER register bit 3 is set while the controller is in Host mode it will generate Reset signaling on the bus If the HSENAB bit in the POWER regis...

Page 1345: ...o establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL is set it indicates that the target did not accept the command for example because it is not supported by the target device and so has issued a STALL response If ERROR is set it means that the controller has tried to send the SETUP Packet and the following data packet three times with...

Page 1346: ...K limit reached No Yes Error count cleared incremented Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete Architecture www ti com 1346 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2...

Page 1347: ...it indicates that the target has issued a STALL response If ERROR is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in HOST_NAKLIMIT0 The controller can then be directed either to cont...

Page 1348: ...unt 3 No Error bit set ReqPkt cleared Error Count cleared Interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete For each IN packet requested in SETUP phase ReqPkt set No ACK sent RxPktRdy set ReqPkt cleared Error Count cleared Interrupt generated Architecture www ti com 1348 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyr...

Page 1349: ...OR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target has issued a STALL response If ERROR bit is set it means that the controller has tried to send the OUT token and the following data packet three times without getting any response If NAK_TIMEOUT is set it means that the controller has received a NAK response to each attempt to send the OUT tok...

Page 1350: ...ceived Yes NAK limit reached No Yes Error count cleared incremented Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete Architecture www ti com 1350 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedbac...

Page 1351: ...hether the RXSTALL bit bit 2 the ERROR bit bit 4 the NAK_TIMEOUT bit bit 7 or RXPKTRDY bit bit 0 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the...

Page 1352: ...eared Interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete Completion of either SETUP phase or OUT data phase No ACK sent RxPktRdy set ReqPkt cleared Error Count cleared Interrupt generated ReqPkt and StatusPkt both set Command could not be completed Architecture www ti com 1352 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback ...

Page 1353: ..._CSR0 to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the STATUS Packet and the following data packet three times without getting any response If NAK_TIMEOUT b...

Page 1354: ...nted Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete TxPktRdy and StatusPkt both set Zero length DATA1 packet sent Architecture www ti com 1354 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback...

Page 1355: ...ST_RXTYPE register for the endpoint that is to be used needs to be programmed as Operating speed in the SPEED bit field bits 7 and 6 Set 10 binary value in the PROT field for bulk transfer Endpoint Number of the target device in RENDPN field This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration The RXMAXP register for the controller en...

Page 1356: ...reports an error by setting the ERROR bit of HOST_RXCSR bit 2 The controller then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_RXCSR register to determine whether the RXPKTRDY RXSTALL ERROR or DATAERR_NAKTIMEOUT bit is set and act accordingly If the DATAERR_NAKTIMEOUT bit is set the controller can be directed either to continue trying this ...

Page 1357: ... transfer Endpoint Number of the target device in TENDPN field This is the endpoint number contained in the OUT Tx endpoint descriptor returned by the target device during enumeration The TXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for...

Page 1358: ... then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_TXCSR register to determine whether the RXSTALL bit 5 ERROR bit 2 or NAK_TIMEOUT bit 7 bit is set and act accordingly If the NAK_TIMEOUT bit is set the controller can be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort ...

Page 1359: ...endpoint 31 2 7 2 4 1 1 Setup Before initiating an Isochronous IN Transactions in Host mode The target function address needs to be set in the RXFUNCADDR register for the selected controller endpoint RXFUNCADDR register is available for all endpoints from EP0 to EP4 The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as Operating speed in the SPEED bit field bits 7 ...

Page 1360: ...ted whenever the endpoint is able to accept another packet in its FIFO This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set endpoint...

Page 1361: ... additional buffering This can be done by using the SOF_PULSE signal from the controller to trigger the loading of the next data packet The SOF_PULSE is generated once per frame microframe The interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR 31 2 8 Communications Port Programming Interface CPPI 4 1 DMA Overview The CPPI DMA module supports the transmission and reception of USB pa...

Page 1362: ...it operations and between the Endpoint FIFOs and the CPPI FIFO for receive operations Mentor USB 2 0 Core This controller is responsible for processing USB bus transfers control bulk interrupt and isochronous It supports 4 transmit and 4 receive endpoints in addition to endpoint 0 control 31 2 8 1 CPPI Terminology The following terms are important in the discussion of DMA CPPI Port A port is the c...

Page 1363: ...d for forwarding a packet from one entity to another for any number of purposes Queue Manager The queue manager is a hardware module that is responsible for accelerating management of the packet queues Packets are added to a packet queue by writing the 32 bit descriptor address to a particular memory mapped location in the Queue Manager module Packets are de queued by reading the same location for...

Page 1364: ...it words in the protocol specific region The CPU initializes this field This is encoded in increments of 4 bytes as 0 0 byte 1 4 bytes 16 64 bytes 17 31 Reserved 21 0 Packet Length The length of the packet in bytes If the Packet Length is less than the sum of the buffer lengths then the packet data will be truncated A Packet Length greater than the sum of the buffers is an error The valid range fo...

Page 1365: ...ve descriptors The Tx DMA will return each buffer in sequence 14 On chip This field indicates whether or not this descriptor is in a region which is in on chip memory space 1 or in external memory 0 13 12 Packet Return Queue Mgr This field indicates which queue manager in the system the descriptor is to be returned to after transmission is complete This field is not altered by the DMA during trans...

Page 1366: ...he Host Buffer Descriptor is identical in size and organization to a Host Packet Descriptor but does not include valid information in the packet level fields and does not include a populated region for protocol specific information The packet level fields is not needed since the SOP descriptor contain this information and additional copy of this data is not needed necessary Host Buffer Descriptors...

Page 1367: ...rved Reserved 14 On chip This field indicates whether or not this descriptor is in a region which is in on chip memory space 1 or in external memory 0 13 12 Packet Return Queue Mgr This field indicates which queue manager in the system the descriptor is to be returned to after transmission is complete This field is not altered by the DMA during transmission or reception and is initialized by the C...

Page 1368: ...n 31 0 Original Buffer 0 Pointer The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer descriptor This value is not overwritten during reception This value is read by the Rx DMA to determine the actual buffer location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is nec...

Page 1369: ... operations The teardown register in the CPPI DMA must be written the corresponding endpoint bit in TEARDOWN of the USB module must be set and the FlushFIFO bit in the Mentor USB controller Tx RxCSR register must be set The following is the Transmit teardown procedure highlighting the steps required to be followed 1 Set the TX_TEARDOWN bit in the CPPI DMA TX channel n global configuration register...

Page 1370: ...int 4 TX submit queues 24 2 TX Completion return queues 26 2 RX Completion return queues 28 36 Unassigned application defined queues 31 2 8 5 1 Queuing Packets Prior to queuing packets the host firmware should construct data buffer as well host packet buffer descriptors within memory that is external to the CPPI 4 1 DMA module Queuing of packets onto a packet queue is accomplished by writing a poi...

Page 1371: ...pletes 31 2 8 5 3 4 Receive Completion Queue Receive ports also use packet queues referred to as receive completion queues to return packets to the port after they have been received Even though non allocated queues can be used for this purpose a total of two dedicated queues Queue 26 and Queue 27 that is to be shared amongst all four transmit ports have been reserved for returning received packet...

Page 1372: ...ned within all memory regions A minimum of four bytes of memory needs to be allocated for each Descriptor defined within all 16 Memory Regions The Queue Manager has the capability of managing up to 16 Memory Regions These Memory Regions are used to store descriptors of variable sizes The total number of Descriptors that can be managed by the Queue Manager should not exceed 16K Each Memory Region h...

Page 1373: ...he more entries that are present for a given channel the bigger the slice of the bandwidth that channel will be given Larger tables can be accommodated to allow for more precision This array can only be written by the Host it cannot be read 2 If the application does not need to use the entire 256 entries firmware can initialize the portion of the 256 entries and indicate the size of the entries us...

Page 1374: ...ed or a valid block on Rx FIFO empty signal is not asserted 3 If the DMA channel is capable of processing a credit to transfer a block the DMA scheduler will issue that credit via the DMA scheduling interface These are the steps a The DMA controller may not be ready to accept the credit immediately and is provided a sched_ready signal which is used to stall the scheduler until it can accept the cr...

Page 1375: ...ues Each queue has a one head descriptor pointer and one completion pointer There are four Tx DMA State registers one for each port channel The following information is stored in the Tx DMA State Tx Queue Head Descriptor Pointer s Tx Completion Pointer s Protocol specific control status port scratchpad 31 2 8 10 2 Receive DMA State Registers The Rx DMA State is a combination of control fields and ...

Page 1376: ...e larger packet into smaller packets where each packet size being USB MaxPktSize except the last packet where its size is less than USB MaxPktSize including zero bytes This implies that multiple USB packets of MaxPktSize will be received and transferred together as a single large DMA transfer and the DMA interrupt is generated only at the end of the complete reception of DMA transfer The protocol ...

Page 1377: ...t size of any Generic RNDIS mode enabled endpoints must be a multiple of 64 bytes Generic RNDIS acceleration should not be enabled for endpoints where the max packet size is not a multiple of 64 bytes Only transparent mode should be used for such endpoints Generic RNDIS DMA Transfer Setup The following will configure all four ports channels for Generic RNDIS DMA Transfer type Disable RNDIS Mode gl...

Page 1378: ...xample Example assumptions The CPPI data buffers are 256 bytes in length The USB endpoint 1 Tx and Rx endpoint 1 size are 512 bytes A single transfer length is 608 bytes The SOP offset is 0 This translates to the following Transmit Case 1 Host Packet Descriptor with Packet Length field of 608 bytes and a Data Buffer of size 256 Bytes linked to the 1st Host Buffer Descriptor First Host Buffer Descr...

Page 1379: ...ated Universal Serial Bus 2 0 USB Controller PPD Pointer to Host Packet Descriptor RXCQ Receive Completion Queue or Receive Return Queue for all Rx EPs use 26 or 27 RXSQ Receive Free Packet Buffer Descriptor Queue or Receive Submit Queue for all Rx EPs use 0 to 15 TXCQ Transmit Completion Queue or Transmit Return Queue for all Tx EPs use 24 or 25 TXSQ Transmit Queue or Transmit Submit Queue for EP...

Page 1380: ... NOTE You can create more BD DB pairs and push them on one of the unassigned queues The firmware can pop a BD DP pair from this chosen queue and can create its HPD or HBDs and pre link them prior to submitting the pointers to the HPD and HBD on to the TXSQ Step 2 CDMA and XDMA transfers packet data into Endpoint FIFO for Tx 1 The Queue Manager informs the CDMAS that the TXSQ is not empty 2 CDMAS c...

Page 1381: ... remaining 32 byte from the data to be transferred in main memory to the CPPI FIFO d The XDMA sees FIFO_empty not asserted and transfers 32 byte block from CPPI FIFO to Endpoint FIFO Step 3 Mentor USB 2 0 Core transmits USB packets for Tx 1 Once the XDMA has transferred enough 64 byte blocks of data from the CPPI FIFO to fill the Endpoint FIFO it signals the Mentor USB 2 0 Core that a TX packet is...

Page 1382: ...BD 1 PBD 2 PBD 0 Head Tail Queue 0 RXSQ Head Tail Queue 26 RXCQ Architecture www ti com 1382 SPRUH91D March 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller 2 The Queue Manager then indicates the status of the TXSQ empty to the CDMAS and the TXCQ to the CPU via an interrupt 31 2 8 12 2 Receive USB D...

Page 1383: ...e 1 The Mentor USB 2 0 Core receives a USB packet from the USB Host and stores it in the Endpoint FIFO 2 It then asserts a DMA_req to the XDMA informing it that data is available in the Endpoint FIFO 3 The XDMA verifies the corresponding CPPI FIFO is not full via the FIFO_full signal then starts transferring 64 byte data blocks from the Endpoint FIFO into the CPPI FIFO Step 3 CDMA transfers data f...

Page 1384: ...pt conditions are generated the host processor is interrupted The software needs to read the different interrupt status registers discussed in later section to determine the source of the interrupt The nine USB interrupt conditions are listed in Table 31 28 Table 31 28 USB Interrupt Conditions Interrupt Description USB 8 DRVVBUS level change USB 7 VBus voltage VBus Valid Threshold VBus error USB 6...

Page 1385: ...de in which it responds to any valid IN token with a NAK 31 2 9 2 TEST_J To enter the Test_J test mode the software should set the TEST_J bit in the TESTMODE register to 1 The USB controller will then go into a mode in which it transmits a continuous J on the bus 31 2 9 3 TEST_K To enter the Test_K test mode the software should set the TEST_K bit in the TESTMODE register to 1 The USB controller wi...

Page 1386: ...er that records the number of bytes received 2 The Endpoint 0 CPU pointer is reset 3 CSR0 TxPktRdy is cleared 4 CSR0 RxPktRdy is set 5 An Endpoint 0 interrupt is generated if enabled The effect of these steps is to make the Endpoint 0 controller act as if the packet loaded into the Tx FIFO has flushed and the same packet received over the USB The data that was loaded in the Tx FIFO can now be read...

Page 1387: ...upt Support The USB peripheral provides the interrupts listed in Table 31 29 to the interrupt distributor module INTD For information on the mapping of interrupts see your device specific data manual Table 31 29 USB Interrupts Event Acronym Source DSP Event 19 USB0_INT USB 2 0 Controller 31 2 12 DMA Event Support The USB is an internal bus master peripheral and does not utilize EDMA events The USB...

Page 1388: ...s CTRLR 0x00000001 Wait until controller is finished with Reset When done it will clear the RESET bit field while usbRegs CTRLR 0x1 1 RESET Hold PHY in Reset BootCfg CFGCHIP2 0x00008000 Hold PHY in Reset Drive Reset for few clock cycles for I 0 i 50 I RESET Release PHY from Reset BootCfg CFGCHIP2 0xFFFF7FFF Release PHY from Reset Configure PHY with the Desired Operation OTGMODE BootCfg CFGCHIP2 0x...

Page 1389: ... interrupts in OTG block usbRegs CTRLR 0xFFFFFFF7 Enable PDR2 0 Interrupt usbRegs INTRTXE 0x1F Enable All Core Tx Endpoints Interrupts EP0 Tx Rx interrupt usbRegs INTRRXE 0x1E Enable All Core Rx Endpoints Interrupts Enable all interrupts in OTG block usbRegs INTMSKSETR 0x01FF1E1F Enable all USB interrupts in MUSBMHDRC usbRegs INTRUSBE 0xFF Enable SUSPENDM so that suspend can be seen UTMI signal CS...

Page 1390: ...s Program Link Ram0 and Link Ram1 Base Size No Link Ram1 Size Register exists Most likely is using the same Size Register used Link Ram1 Base usbRegs QMGR LRAM0BASE Uint32 queueMgrLinkRam0 usbRegs QMGR LRAM0SIZE LINKRAM0SIZE 4 usbRegs QMGR LRAM1BASE Uint32 queueMgrLinkRam1 Allocate Resource to Region 0 can use any of the 16 available memory location for Host Packet Descriptors DESC_SIZE value shou...

Page 1391: ...to be programmed Since Queues 0 to 15 are alloted for Receive operations and there exist no dedicated queue assignments for each channel a user can associate any Queue with any Channel and this association is not fixed for the Receive Operations Queue 15 0 Any Rx Channel However for Tx Operations Dedicated Submit Queues have been assigned for Each Channel Endpoints Queue 17 16 TxCh 0 Queue 19 18 T...

Page 1392: ...buffer 1 Double buffer For maximum packet size this formula will usually work but it can also be set to another value if needed If non power of 2 value is needed such as 1023 set it explicitly define FIFO_MAXP 8 1 fifosize Set the following variable to the device address int device_address 0 The following code should be run after receiving a USB reset from the host Initialize the endpoint FIFO RX ...

Page 1393: ... If double buffer is selected actual FIFO space will be twice the value listed above for fifosize This example uses single buffer int double_buffer 0 Single buffer int double_buffer 1 Double buffer Set the following variable to the device endpoint type CONTROL ISO BULK or IN int device_protocol BULK int device_protocol ISO int device_protocol INT USB speeds define LOW_SPEED 0 define FULL_SPEED 1 d...

Page 1394: ...ED type 3 6 device_protocol 3 4 device_ep 0xf break case FULL_SPEED type 2 6 device_protocol 3 4 device_ep 0xf break case HIGH_SPEED type 1 6 device_protocol 3 4 device_ep 0xf break default error usbRegs EPCSR CHAN_NUM 1 HOST_TYPE0 type TXTYPE usbRegs EPCSR CHAN_NUM 1 HOST_RXTYPE type Set NAK limit Polling interval Interrupt Iso protocols if device_protocol INT device_protocol ISO usbRegs EPCSR CH...

Page 1395: ...t32 Rsv 6 bits 25 20 Uint32 PktType 5 bits 30 26 Uint32 PktErr 1 bit 31 HPDWord2 typedef struct hostPacketDesc HPDWord0 HPDword0 HPDWord1 HPDword1 HPDWord2 HPDword2 Uint32 HPDword3buffLength Uint32 HPDword4buffAdd Uint32 HPDword5nextHBDptr Uint32 HPDword6orgBuffLength Uint32 HPDword7orgBuffAdd HostPacketDesc The following sample code uses region 0 for all of the ports Ports Channels EPs are not li...

Page 1396: ...stTag 0 Always programmed to ZERO region0DescriptorSpace descNum HPDword1 SrcSubChNum 0 Always programmed to ZERO region0DescriptorSpace descNum HPDword1 SrcChNum 0 Always programmed to ZERO if desc BUFFER_DESC region0DescriptorSpace descNum HPDword1 SrcPrtNum 0 Word1 is Reserved for Buffer DESC else region0DescriptorSpace descNum HPDword1 SrcPrtNum chan_num 1 Ports 1 2 3 4 is associated with Endp...

Page 1397: ...Length prevDescRxNum if dir TRANSMIT prevDescTxNum 1 0 region0DescriptorSpace descNum 1 HPDword5nextHBDptr Uint32 region0DescriptorSpace descNum Modify Previous Link Address region0DescriptorSpace descNum HPDword5nextHBDptr 0 Current Descriptor is the Last Descriptor Null Value is used as the Next Buffer Descriptor Address region0DescriptorSpace descNum HPDword6orgBuffLength region0DescriptorSpace...

Page 1398: ... txSubmitQ etc wait_for_reset wait here until host performs a reset cppiDmaInit Init CPPI 4 1 DMA Initialize Receive Buffer Descriptors Host is performing a transfer and the device is going to loop it back out The example below non commented part of the code applies for a data transfer made of two 64 bytes packet These two packets are treated as part of a single transfer for Non Transparent DMA mo...

Page 1399: ...initSingleHPDorHBD 19 TRANSMIT PACKET_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue else initSingleHPDorHBD 17 TRANSMIT BUFFER_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue initSingleHPDorHBD 18 TRANSMIT BUFFER_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue initSingleHPDorHBD 19 TRANSMIT BUFFER_DESC txCompQ Usage initS...

Page 1400: ...ter Section 31 4 10 28h INTCLRR USB Interrupt Source Clear Register Section 31 4 11 2Ch INTMSKR USB Interrupt Mask Register Section 31 4 12 30h INTMSKSETR USB Interrupt Mask Set Register Section 31 4 13 34h INTMSKCLRR USB Interrupt Mask Clear Register Section 31 4 14 38h INTMASKEDR USB Interrupt Source Masked Register Section 31 4 15 3Ch EOIR USB End of Interrupt Register Section 31 4 16 50h GENRN...

Page 1401: ...t Endpoint 0 Section 31 4 40 RXCOUNT Number of Bytes in Host Receive Endpoint FIFO Index register set to select Endpoints 1 4 Section 31 4 41 41Ah HOST_TYPE0 Defines the speed of Endpoint 0 Section 31 4 42 HOST_TXTYPE Sets the operating speed transaction protocol and peripheral endpoint number for the host Transmit endpoint Index register set to select Endpoints 1 4 only Section 31 4 43 41Bh HOST_...

Page 1402: ...s of the target function that has to be accessed through the associated Receive Endpoint Section 31 4 63 486h RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Section 31 4 64 487h RXHUBPORT Port of the hub that has to be accessed through the associated Receive ...

Page 1403: ...that has to be accessed through the associated Transmit Endpoint Section 31 4 60 49Ah TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Section 31 4 61 49Bh TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint This is used ...

Page 1404: ...m Packet Size for Peripheral Host Receive Endpoint Section 31 4 37 516h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint peripheral mode Section 31 4 38 HOST_RXCSR Control Status Register for Host Receive Endpoint host mode Section 31 4 39 518h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 31 4 41 51Ah HOST_TXTYPE Sets the operating speed transaction protocol and ...

Page 1405: ...t Section 31 4 43 53Bh HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint Section 31 4 45 53Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral endpoint number for the host Receive endpoint Section 31 4 46 53Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC trans...

Page 1406: ...nfiguration Register Section 31 4 69 1868h RXGCR 3 Receive Channel 3 Global Configuration Register Section 31 4 70 186Ch RXHPCRA 3 Receive Channel 3 Host Packet Configuration Register A Section 31 4 71 1870h RXHPCRB 3 Receive Channel 3 Host Packet Configuration Register B Section 31 4 72 2000h DMA_SCHED_CTRL CDMA Scheduler Control Register Section 31 4 73 2800h 28FCh WORD 0 WORD 63 CDMA Scheduler ...

Page 1407: ...CTRLR allows the CPU to control various aspects of the module The CTRLR is shown in Figure 31 28 and described in Table 31 32 Figure 31 28 Control Register CTRLR 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved RNDIS UINT Reserved CLKFACK RESET R 0 R W 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 32 Control Register CTRLR Field Descriptions Bit Field Value Descr...

Page 1408: ...it Field Value Description 31 1 Reserved 0 Reserved 0 DRVVBUS Current DRVVBUS value 0 DRVVBUS value is logic 0 1 DRVVBUS value is logic 1 31 4 4 Emulation Register EMUR The emulation register EMUR allows the CPU to configure the CBA 3 0 emulation interface The EMUR is shown in Figure 31 30 and described in Table 31 34 Figure 31 30 Emulation Register EMUR 31 16 Reserved R 0 15 3 2 1 0 Reserved RT_S...

Page 1409: ...served 0 Reserved 29 28 RX4_MODE 0 3h Receive endpoint 4 mode control 0 Transparent mode on Receive endpoint 4 1h RNDIS mode on Receive endpoint 4 2h CDC mode on Receive endpoint 4 3h Generic RNDIS mode on Receive endpoint 4 27 26 Reserved 0 Reserved 25 24 RX3_MODE 0 3h Receive endpoint 3 mode control 0 Transparent mode on Receive endpoint 3 1h RNDIS mode on Receive endpoint 3 2h CDC mode on Recei...

Page 1410: ...IS mode on Transmit endpoint 3 2h CDC mode on Transmit endpoint 3 3h Generic RNDIS mode on Transmit endpoint 3 7 6 Reserved 0 Reserved 5 4 TX2_MODE 0 3h Transmit endpoint 2 mode control 0 Transparent mode on Transmit endpoint 2 1h RNDIS mode on Transmit endpoint 2 2h CDC mode on Transmit endpoint 2 3h Generic RNDIS mode on Transmit endpoint 2 3 2 Reserved 0 Reserved 1 0 TX1_MODE 0 3h Transmit endp...

Page 1411: ...n the CPPI descriptor For RNDIS CDC and Generic RNDIS modes the auto request stops when the EOP is received either via a short packet for RNDIS CDC and Generic RNDIS or the count is reached for Generic RNDIS making it useful for starting a large RNDIS packet and having it auto generate IN tokens until the end of the RNDIS packet For transparent mode every USB packet is an EOP CPPI packet so the au...

Page 1412: ...rols the tearing down of receive and transmit FIFOs in the USB controller When a 1 is written to a valid bit in TEARDOWN the CPPI FIFO pointers for that endpoint are cleared TEARDOWN must be used in conjunction with the CPPI DMA teardown mechanism The Host should also write the FLUSHFIFO bits in the TXCSR and RXCSR registers to ensure a complete teardown of the endpoint The TEARDOWN is shown in Fi...

Page 1413: ...ved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 39 USB Interrupt Source Register INTSRCR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh USB interrupt sources Generated by the USB core not by the DMA Note INTRUSB core interrupts are mapped onto bits 23 16 and bit 2...

Page 1414: ...ETR 31 25 24 16 Reserved USB R 0 R W 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 40 USB Interrupt Source Set Register INTSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt source Allows the USB interrupt source...

Page 1415: ... W 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 41 USB Interrupt Source Clear Register INTCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt source Allows the CPU to acknowledge a USB interrupt source and turn...

Page 1416: ...in CTRLR is set to 1 you need to use the interrupt status flag from the core register space Figure 31 38 USB Interrupt Mask Register INTMSKR 31 25 24 16 Reserved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 42 USB Interrupt Mask Register INTMSKR Field Descriptions Bit Field Value Description 31 25 Reserved ...

Page 1417: ...12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 43 USB Interrupt Mask Set Register INTMSKSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt source mask Allows the USB interrupt source masks to be manually enabled 15 13 Res...

Page 1418: ... 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 44 USB Interrupt Mask Clear Register INTMSKCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt source mask Allows the USB interrupt source masks to be manually disabled 15 13 ...

Page 1419: ... you need to use the interrupt status flag from the core register space Figure 31 41 USB Interrupt Source Masked Register INTMASKEDR 31 25 24 16 Reserved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 45 USB Interrupt Source Masked Register INTMASKEDR Field Descriptions Bit Field Value Description 31 25 Reser...

Page 1420: ...or 31 4 17 Generic RNDIS EP1 Size Register GENRNDISSZ1 The generic RNDIS EP1 size register GENRNDISSZ1 is programmed with a RNDIS packet size in bytes When EP1 is in Generic RNDIS mode the received USB packets are collected into a single CPPI packet that is completed when the number of bytes equal to the value of this register have been received or a short packet is received This register must be ...

Page 1421: ... value after reset Table 31 48 Generic RNDIS EP2 Size Register GENRNDISSZ2 Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 0 EP2_SIZE 0 10000h Generic RNDIS packet size 31 4 19 Generic RNDIS EP3 Size Register GENRNDISSZ3 The generic RNDIS EP3 size register GENRNDISSZ3 is programmed with a RNDIS packet size in bytes When EP3 is in Generic RNDIS mode the received USB pack...

Page 1422: ...ed EP4_SIZE R 0 R W 0 15 0 EP4_SIZE R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 50 Generic RNDIS EP4 Size Register GENRNDISSZ4 Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 0 EP4_SIZE 0 10000h Generic RNDIS packet size 31 4 21 Function Address Register FADDR The function address register FADDR is shown in Figure 31 47 and described in Table 31...

Page 1423: ...ONN 0 1 If Soft Connect Disconnect feature is enabled then the USB D D lines are enabled when this bit is set and tri stated when this bit is cleared Note this is only valid in Peripheral Mode 5 HSEN 0 1 When set the USB controller will negotiate for high speed mode when the device is reset by the hub If not set the device will only operate in full speed mode 4 HSMODE 0 1 This bit is set when the ...

Page 1424: ...read clears the pending interrupt Use INTRTX only when in the non PDR interrupt mode that is when handling the interrupt directly from the controller Figure 31 49 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 INTRTX 15 8 Reserved R 0 7 5 4 3 2 1 0 Reserved EP4TX EP3TX EP2TX EP1TX EP0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 53 Interrupt Register for Endp...

Page 1425: ...ming a read clears the pending interrupt Use INTRRX only when in the non PDR interrupt mode that is when handling the interrupt directly from the controller Figure 31 50 Interrupt Register for Receive Endpoints 1 to 4 INTRRX 15 8 Reserved R 0 7 5 4 3 2 1 0 Reserved EP4RX EP3RX EP2RX EP1RX Rsvd R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 54 Interrupt Register for Receive...

Page 1426: ... 4 interrupt active 3 EP3TX 0 1 Transmit Endpoint 3 interrupt active 2 EP2TX 0 1 Transmit Endpoint 2 interrupt active 1 EP1TX 0 1 Transmit Endpoint 1 interrupt active 0 EP0 0 1 Endpoint 0 interrupt active 31 4 26 Interrupt Enable Register for INTRRX INTRRXE The interrupt enable register for INTRRX INTRRXE is shown in Figure 31 52 and described in Table 31 56 Figure 31 52 Interrupt Enable Register ...

Page 1427: ...R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 57 Interrupt Register for Common USB Interrupts INTRUSB Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Set when VBus drops below the VBus valid threshold during a session Only valid when the USB controller is A device All active interrupts will be cleared when this register is read 6 SESSREQ 0 1 Set when session request ...

Page 1428: ...egister for INTRUSB INTRUSBE Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Vbus error interrupt enable 6 SESSREQ 0 1 Session request interrupt enable 5 DISCON 0 1 Disconnect interrupt enable 4 CONN 0 1 Connect interrupt enable 3 SOF 0 1 Start of frame interrupt enable 2 RESET_BABBLE 0 1 Reset interrupt enable 1 RESUME 0 1 Resume interrupt enable 0 SUSPEND 0 1 Suspend interrupt enabl...

Page 1429: ...EGEND R W Read Write W Write only n value after reset Table 31 61 Register to Enable the USB 2 0 Test Modes TESTMODE Field Descriptions Bit Field Value Description 7 FORCE_HOST 0 1 Set this bit to forcibly put the USB controller into Host mode when SESSION bit is set regardless of whether it is connected to any peripheral The controller remains in Host mode until the Session bit is cleared even if...

Page 1430: ...AXPAYLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 62 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD 0 400h The maximum payload transmitted in a single transaction The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specifi...

Page 1431: ... RXPKTRDY is set 7 SERV_SETUPEND 0 1 Set this bit to clear the SETUPEND bit It is cleared automatically 6 SERV_RXPKTRDY 0 1 Set this bit to clear the RXPKTRDY bit It is cleared automatically 5 SENDSTALL 0 1 Set this bit to terminate the current transaction The STALL handshake will be transmitted and then this bit will be cleared automatically 4 SETUPEND 0 1 This bit will be set when a control tran...

Page 1432: ...OGWREN is low any value written to this bit is ignored 8 FLUSHFIFO 0 1 Write 1 to this bit to flush the next packet to be transmitted read from the Endpoint 0 FIFO The FIFO pointer is reset and the TXPKTRDY RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless TXPKTRDY RXPKTRDY is set 7 NAK_TIMEOUT 0 1 This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for ...

Page 1433: ...ly where the same endpoint FIFO is used for both Transmit and Receive transactions 12 DMAEN 0 1 Set this bit to enable the DMA request for the Tx endpoint 11 FRCDATATOG 0 1 Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO regardless of whether an ACK was received This can be used by Interrupt Tx endpoints that are used to communicate rate fee...

Page 1434: ...MODE 0 1 This bit should always be set to 1 when the DMA is enabled 9 DATATOGWREN 0 1 Write 1 to this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 8 DATATOG 0 1 When read this bit indicates the current state of the Tx EP data toggle If DATATOGWREN is high this bit can be written with the required setting of the data toggle I...

Page 1435: ...ad only n value after reset Table 31 67 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD 0 400h Defines the maximum amount of data that can be transferred through the selected Receive endpoint in a single frame microframe high speed transfers The value set can be up to 1024 bytes but is subject ...

Page 1436: ... are ACK d including at the point at which the FIFO becomes full Note This bit only has any effect in high speed mode in which mode it should be set for all Interrupt endpoints 1 PID_ERROR Applies only for ISO Transactions The core sets this bit to indicate a PID error in the received packet 11 DMAMODE 0 1 Always clear this bit to 0 10 8 Reserved 0 Reserved 7 CLRDATATOG 0 1 Write a 1 to this bit t...

Page 1437: ... which mode it should be set for all Interrupt endpoints 11 DMAMODE 0 1 Always clear this bit to 0 10 DATATOGWREN 0 1 Write 1 to this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 9 DATATOG 0 1 When read this bit indicates the current state of the Receive EP data toggle If DATATOGWREN is high this bit can be written with the ...

Page 1438: ...ue after reset Table 31 70 Count 0 Register COUNT0 Field Descriptions Bit Field Value Description 15 7 Reserved 0 Reserved 6 0 EP0RXCOUNT 0 7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSR0 or HOST_CSR0 is set 31 4 41 Receive Count Register RXCOUNT The receive count regi...

Page 1439: ... High 2h Full 3h Low 5 0 Reserved 0 Reserved 31 4 43 Transmit Type Register Host mode only HOST_TXTYPE The transmit type register Host mode only HOST_TXTYPE is shown in Figure 31 69 and described in Table 31 73 Figure 31 69 Transmit Type Register Host mode only HOST_TXTYPE 7 6 5 4 3 0 SPEED PROT TENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 31 73 Transmit Type Register H...

Page 1440: ...t function 31 4 45 Transmit Interval Register Host mode only HOST_TXINTERVAL The transmit interval register Host mode only HOST_TXINTERVAL is shown in Figure 31 71 and described in Table 31 75 Figure 31 71 Transmit Interval Register Host mode only HOST_TXINTERVAL 7 0 POLINTVL_NAKLIMIT R W 0 LEGEND R W Read Write n value after reset Table 31 75 Transmit Interval Register Host mode only HOST_TXINTER...

Page 1441: ... Host mode only HOST_RXTYPE 7 6 5 4 3 0 SPEED PROT RENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 31 76 Receive Type Register Host mode only HOST_RXTYPE Field Descriptions Bit Field Value Description 7 6 SPEED 0 3h Operating Speed of Target Device 0 Illegal 1h High 2h Full 3h Low 5 4 PROT 0 3h Set this to select the required protocol for the transmit endpoint 0 Control 1h...

Page 1442: ...IMIT 0 FFh For Interrupt and Isochronous transfers defines the polling interval for the currently selected transmit endpoint For Bulk endpoints sets the number of frames microframes after which the endpoint should timeout on receiving a stream of NAK responses There is a transmit interval register for each configured transmit endpoint except Endpoint 0 In each case the value that is set defines a ...

Page 1443: ...mation of bulk packets is selected 6 MPTXE Indicates automatic splitting of bulk packets 0 Automatic splitting of bulk packets is not selected 1 Automatic splitting of bulk packets is selected 5 BIGENDIAN Indicates endian ordering 0 Little endian ordering is selected 1 Big endian ordering is selected 4 HBRXE Indicates high bandwidth Rx ISO endpoint support 0 High bandwidth Rx ISO endpoint support ...

Page 1444: ...FFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 31 4 50 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 The transmit and receive FIFO register for endpoint 1 FIFO1 is shown in Figure 31 76 and described in Table 31 80 Figure 31 76 Transmit and...

Page 1445: ...FF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 31 4 52 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 The transmit and receive FIFO register for endpoint 3 FIFO3 is shown in Figure 31 78 and described in Table 31 82 Figure 31 78 Transmit and ...

Page 1446: ...ption 7 BDEVICE This read only bit indicates whether the USB controller is operating as the A device or the B device 0 A device 1 B device Only valid while a session is in progress 6 FSDEV 0 1 This read only bit is set when a full speed or high speed device has been detected being connected to the port high speed devices are distinguished from full speed by checking for high speed chirps when the ...

Page 1447: ...to be allowed before any splitting within the FIFO of Bulk packets prior to transmission If m SZ the FIFO size is calculated as 2 m 3 for single packet buffering and 2 m 4 for dual packet buffering 31 4 56 Receive Endpoint FIFO Size RXFIFOSZ Section 31 2 6 describes dynamically setting endpoint FIFO sizes The option of dynamically setting endpoint FIFO sizes only applies to Endpoints 1 4 The Endpo...

Page 1448: ...ress TXFIFOADDR Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12 0 ADDR 0 1FFFh Start Address of endpoint FIFO in units of 8 bytes If m ADDR then the start address is 8 m 31 4 58 Receive Endpoint FIFO Address RXFIFOADDR Section 31 2 6 describes dynamically setting endpoint FIFO sizes The receive endpoint FIFO address RXFIFOADDR is shown in Figure 31 84 and described in T...

Page 1449: ...ler module The RTL version number is REVMAJ REVMIN The HWVERS is shown in Figure 31 85 and described in Table 31 89 Figure 31 85 Hardware Version Register HWVERS 15 14 10 9 0 RC REVMAJ REVMIN R 0 R 0 R 0 LEGEND R Read only n value after reset Table 31 89 Hardware Version Register HWVERS Field Descriptions Bit Field Value Description 15 RC 0 1 Set to 1 if RTL is used from a Release Candidate rather...

Page 1450: ...transmit hub address TXHUBADDR is shown in Figure 31 87 and described in Table 31 91 Figure 31 87 Transmit Hub Address TXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 91 Transmit Hub Address TXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only...

Page 1451: ...he receive hub address RXHUBADDR is shown in Figure 31 90 and described in Table 31 94 Figure 31 90 Receive Hub Address RXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 94 Receive Hub Address RXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only...

Page 1452: ...iptor queue control register TDFDQ is used to inform the DMA of the location in memory or descriptor array which is to be used for signaling of a teardown complete for each transmit and receive channel The CDMA teardown free descriptor queue control register TDFDQ is shown in Figure 31 93 and described in Table 31 97 Figure 31 93 CDMA Teardown Free Descriptor Queue Control Register TDFDQ 31 16 Res...

Page 1453: ... Transmit Channel n Global Configuration Registers TXGCR 0 TXGCR 3 The transmit channel n configuration registers TXGCR n initialize the behavior of each of the transmit DMA channels There are four configuration registers one for each transmit DMA channels The transmit channel n configuration registers TXGCR n are shown in Figure 31 95 and described in Table 31 99 Figure 31 95 CDMA Transmit Channe...

Page 1454: ...after a channel teardown is complete 29 25 Reserved 0 Reserved 24 RX_ERROR_HANDLING Controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occur 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in ...

Page 1455: ..._FDQ1_QNUM R 0 W 0 W 0 15 14 13 12 11 0 Reserved RX_HOST_FDQ0_QMGR RX_HOST_FDQ0_QNUM R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 31 101 Receive Channel n Host Packet Configuration Registers A RXHPCRA n Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 28 RX_HOST_FDQ1_QMGR 0 3h Specifies which buffer manager should be used for the second receive b...

Page 1456: ... 0 W 0 15 14 13 12 11 0 Reserved RX_HOST_FDQ2_QMGR RX_HOST_FDQ2_QNUM R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 31 102 Receive Channel n Host Packet Configuration Registers B RXHPCRB n Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 28 RX_HOST_FDQ3_QMGR 0 3h Specifies which buffer manager should be used for the fourth or later receive buffer i...

Page 1457: ...tialized 30 8 Reserved 0 Reserved 7 0 LAST_ENTRY 0 FFh Indicates the last valid entry in the scheduler table There are 64 words in the table and there are 4 entries in each word The table can be programmed with any integer number of entries from 1 to 256 The corresponding encoding for this field is as follows 0 1 entry 1h 2 entries 2h FFh 3 entries to 256 entries 31 4 74 CDMA Scheduler Table Word ...

Page 1458: ... in the receive credit will actually be the channel number which is currently on the head element of that Rx FIFO which is not necessarily the channel number given in the scheduler table entry 15 ENTRY1_RXTX This entry is for a transmit or a receive channel 0 Transmit channel 1 Receive channel 14 12 Reserved 0 Reserved 11 8 ENTRY1_CHANNEL 0 Fh Indicates the channel number that is to be given an op...

Page 1459: ... of the queue manager 31 4 76 Queue Manager Queue Diversion Register DIVERSION The queue manager queue diversion register DIVERSION is used to transfer the contents of one queue onto another queue It does not support byte accesses The queue manager queue diversion register DIVERSION is shown in Figure 31 102and described in Table 31 106 Figure 31 102 Queue Manager Queue Diversion Register DIVERSIO...

Page 1460: ...4 23 16 FDBQ3_STARVE_CNT FDBQ2_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ1_STARVE_CNT FDBQ0_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 31 107 Queue Manager Free Descriptor Buffer Starvation Count Register 0 FDBSC0 Field Descriptions Bit Field Value Description 31 24 FDBQ3_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 3 is read while it is e...

Page 1461: ... 24 23 16 FDBQ7_STARVE_CNT FDBQ6_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ5_STARVE_CNT FDBQ4_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 31 108 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 Field Descriptions Bit Field Value Description 31 24 FDBQ7_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 7 is read while it is...

Page 1462: ...4 23 16 FDBQ11_STARVE_CNT FDB10_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ9_STARVE_CNT FDBQ8_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 31 109 Queue Manager Free Descriptor Buffer Starvation Count Register 2 FDBSC2 Field Descriptions Bit Field Value Description 31 24 FDBQ11_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 11 is read while it i...

Page 1463: ...each time the Free Descriptor Buffer Queue 14 is read while it is empty This field is cleared when read 15 8 FDBQ13_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 13 is read while it is empty This field is cleared when read 7 0 FDBQ12_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 12 is read while it is empty This field is clear...

Page 1464: ...with index less than region0_size value has its linking location in region 0 A descriptor with index greater than region0_size has its linking location in region 1 The queue manager will add the index left shifted by 2 bits to the appropriate regionX_base_addr to get the absolute 32 bit address to the linking location for a descriptor 31 4 83 Queue Manager Linking RAM Region 1 Base Address Registe...

Page 1465: ...et Table 31 114 Queue Manager Queue Pending Register 0 PEND0 Field Descriptions Bit Field Value Description 31 0 QPEND0 0 FFFF FFFFh This field indicates the queue pending status for queues 31 0 31 4 85 Queue Manager Queue Pending Register 1 PEND1 The queue pending register 1 PEND1 can be read to find the pending status for queues 63 to 32 It does not support byte accesses The queue pending regist...

Page 1466: ...his memory region will store a number of descriptors of a particular size as determined by the memory region R control register It does not support byte accesses The memory region R base address register QMEMRBASE R is shown in Figure 31 112 and described in Table 31 116 Figure 31 112 Queue Manager Memory Region R Base Address Registers QMEMRBASE R 31 0 REG R W 0 LEGEND R W Read Write n value afte...

Page 1467: ...1 30 29 16 Reserved START_INDEX R 0 R W 0 15 12 11 8 7 3 2 0 Reserved DESC_SIZE Reserved REG_SIZE R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 117 Queue Manager Memory Region R Control Registers QMEMRCTRL R Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 16 START_INDEX 0 3FFFh This field indicates where in linking RAM the descriptor...

Page 1468: ...not support byte accesses The queue manager queue N control register D CTRLD N is shown in Figure 31 114 and described in Table 31 118 Figure 31 114 Queue Manager Queue N Control Register D CTRLD N 31 16 DESC_PTR R W 0 15 5 4 0 DESC_PTR DESC_SIZE R W 0 R W 0 LEGEND R W Read Write n value after reset Table 31 118 Queue Manager Queue N Control Register D CTRLD N Field Descriptions Bit Field Value De...

Page 1469: ...Bit Field Value Description 31 14 Reserved 0 Reserved 13 0 QUEUE_ENTRY_COUNT 0 3FFFh This field indicates how many packets are currently queued on the queue 31 4 90 Queue Manager Queue N Status Register B QSTATB 0 QSTATB 63 The queue manager queue N status register B QSTATB N is an optional register that is only implemented for a queue if the queue supports a total byte count feature The total byt...

Page 1470: ...ement of a queue It does not support byte accesses The queue manager queue N status register C QSTATC N is shown in Figure 31 117 and described in Table 31 121 Figure 31 117 Queue Manager Queue N Status Register C QSTATC N 31 16 Reserved R 0 15 14 13 0 Reserved PACKET_SIZE R 0 R 0 LEGEND R Read only n value after reset Table 31 121 Queue Manager Queue N Status Register C QSTATC N Field Description...

Page 1471: ...pyright 2013 2016 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from July 1 2016 to September 21 2016 from C Revision July 2016 to D Revision Page Updated GMIIEN bit in Section 17 3 3 29 672 ...

Page 1472: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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