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SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
20-19. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01)
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20-20. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23)
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20-21. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45)
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20-22. GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67)
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20-23. GPIO Bank 8 Clear Data Register (CLR_DATA8)
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20-24. GPIO Banks 0 and 1 Input Data Register (IN_DATA01)
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20-25. GPIO Banks 2 and 3 Input Data Register (IN_DATA23)
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20-26. GPIO Banks 4 and 5 Input Data Register (IN_DATA45)
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20-27. GPIO Banks 6 and 7 Input Data Register (IN_DATA67)
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20-28. GPIO Bank 8 Input Data Register (IN_DATA8)
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20-29. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01)
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20-30. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23)
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20-31. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45)
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20-32. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67)
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20-33. GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8)
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20-34. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01)
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20-35. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23)
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20-36. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45)
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20-37. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67)
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20-38. GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8)
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20-39. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01)
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20-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23)
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20-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45)
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20-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67)
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20-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8)
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20-44. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01)
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20-45. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23)
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20-46. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45)
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20-47. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67)
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20-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8)
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20-49. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01)
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20-50. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23)
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20-51. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45)
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20-52. GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67)
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20-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8)
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21-1.
HPI Block Diagram
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21-2.
Example of Host-Processor Signal Connections
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21-3.
HPI Strobe and Select Logic
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21-4.
Multiplexed-Mode Host Read Cycle
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21-5.
Multiplexed-Mode Host Write Cycle
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21-6.
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write)
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21-7.
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode
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21-8.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle)
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21-9.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles)
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21-10. UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode
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21-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1:
No Autoincrementing)
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21-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2: