12
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
22.3.16
I2C Pin Function Register (ICPFUNC)
....................................................................
22.3.17
I2C Pin Direction Register (ICPDIR)
.......................................................................
22.3.18
I2C Pin Data In Register (ICPDIN)
.........................................................................
22.3.19
I2C Pin Data Out Register (ICPDOUT)
....................................................................
22.3.20
I2C Pin Data Set Register (ICPDSET)
....................................................................
22.3.21
I2C Pin Data Clear Register (ICPDCLR)
..................................................................
23
Liquid Crystal Display Controller (LCDC)
.............................................................................
23.1
Introduction
................................................................................................................
23.1.1
Purpose of the Peripheral
.....................................................................................
23.1.2
Features
..........................................................................................................
23.1.3
Terminology
.....................................................................................................
23.2
Architecture
................................................................................................................
23.2.1
Clocking
..........................................................................................................
23.2.2
LCD External I/O Signals
......................................................................................
23.2.3
DMA Engine
.....................................................................................................
23.2.4
LIDD Controller
..................................................................................................
23.2.5
Raster Controller
................................................................................................
23.3
Registers
...................................................................................................................
23.3.1
LCD Revision Identification Register (REVID)
..............................................................
23.3.2
LCD Control Register (LCD_CTRL)
..........................................................................
23.3.3
LCD Status Register (LCD_STAT)
...........................................................................
23.3.4
LCD LIDD Control Register (LIDD_CTRL)
..................................................................
23.3.5
LCD LIDD CS
n
Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF)
................
23.3.6
LCD LIDD CS
n
Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR)
........
23.3.7
LCD LIDD CS
n
Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA)
.............
23.3.8
LCD Raster Control Register (RASTER_CTRL)
............................................................
23.3.9
LCD Raster Timing Register 0 (RASTER_TIMING_0)
....................................................
23.3.10
LCD Raster Timing Register 1 (RASTER_TIMING_1)
...................................................
23.3.11
LCD Raster Timing Register 2 (RASTER_TIMING_2)
...................................................
23.3.12
LCD Raster Subpanel Display Register (RASTER_SUBPANEL)
......................................
23.3.13
LCD DMA Control Register (LCDDMA_CTRL)
............................................................
23.3.14
LCD DMA Frame Buffer
n
Base Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE)
........................................................
23.3.15
LCD DMA Frame Buffer
n
Ceiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING)
.................................................
24
Multichannel Audio Serial Port (McASP)
..............................................................................
24.0.16
Features
.......................................................................................................
24.0.17
Protocols Supported
.........................................................................................
24.0.18
Functional Block Diagram
....................................................................................
24.0.19
Definition of Terms
...........................................................................................
24.0.20
Overview
.......................................................................................................
24.0.21
Clock and Frame Sync Generators
........................................................................
24.0.22
Reset Considerations
.......................................................................................
24.0.23
EDMA Event Support
.......................................................................................
24.0.24
Power Management
.........................................................................................
24.1
Registers
.................................................................................................................
24.1.1
Register Bit Restrictions
......................................................................................
24.1.2
Revision Identification Register (REV)
.....................................................................
24.1.3
Pin Function Register (PFUNC)
.............................................................................
24.1.4
Pin Direction Register (PDIR)
...............................................................................
24.1.5
Pin Data Output Register (PDOUT)
........................................................................
24.1.6
Pin Data Input Register (PDIN)
..............................................................................
24.1.7
Pin Data Set Register (PDSET)
.............................................................................