PLLC Registers
125
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Phase-Locked Loop Controller (PLLC)
7.4.5 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in
and described in
Figure 7-6. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 7-7. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
Value
Description
31-5
Reserved
0
Reserved
4-0
PLLM
0-1Fh
PLL Multiplier Select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
7.4.6 PLL Pre-Divider Control Register (PREDIV)
The PLL pre-divider control register (PREDIV) is shown in
and described in
.
Figure 7-7. PLL Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 7-8. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
Value
Description
31-14
Reserved
0
Reserved
15
PREDEN
Pre_Divider enable.
0
Disable
1
Enable
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).