Architecture
789
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
Table 19-6. Description of the SDRAM Configuration Register (SDCFG) (continued)
Parameter
Description
PAGESIZE
Page Size.
This field defines the internal page size of the attached SDRAM devices in the following
way:
• When PAGESIZE = 0, 256-word pages are used, requiring 8 column address bits.
• When PAGESIZE = 1h, 512-word pages are used, requiring 9 column address bits.
• When PAGESIZE = 2h, 1024-word pages are used, requiring 10 column address bits.
• When PAGESIZE = 3h, 2048-word pages are used, requiring 11 column address bits.
This field value affects the mapping of logical addresses to SDRAM row, column, and bank
addresses. See
for details.
Table 19-7. Description of the SDRAM Refresh Control Register (SDRFC)
Parameter
Description
LP_MODE
Low Power Mode
. This bit enables the self-refresh mode of the attached SDRAM devices (which is
the lowest power mode).
MCLKSTOP_EN
mclk stop enable.
mclk can stopped only if this bit is set.
SR_PD
Self Refresh/ Power Down select.
This bit along with LP_MODE determines if SDRAM is to be
placed in self-refresh/power-down mode.
REFRESH_RATE
Refresh Rate
. This field controls the rate at which attached SDRAM devices will be refreshed. The
following equation can be used to determine the required value of REFRESH_RATE for an SDRAM
device:
• REFRESH_RATE = (EMIFB clock rate)/(Required SDRAM Refresh Rate)
More information about the operation of the SDRAM refresh controller can be found in
Table 19-8. Description of the SDRAM Timing 1 Register (SDTIM1)
Parameter
Description
T_RFC
SDRAM Timing Parameters.
These fields configure the EMIFB to comply with the AC timing
requirements of the attached SDRAM devices. This allows the EMIFB to avoid violating SDRAM
timing constraints and to more efficiently schedule its operations. More details about each of these
parameters can be found in the register description in
. These parameters are set to
satisfy the corresponding timing requirements found in the SDRAM's datasheet.
T_RP
T_RCD
T_WR
T_RAS
T_RC
T_RRD
Table 19-9. Description of the SDRAM Timing 2 Register (SDTIM2)
Parameter
Description
T_RAS_MAX
Maximum number of refresh_rate intervals from Activate to Precharge command.
T_XS
Self Refresh Exit Parameter.
The T_XS field of this register informs the EMIFB about the minimum
number of EMB_CLK cycles required between exiting Self Refresh and issuing any command. This
parameter is set to satisfy the t
XSR
value for the attached SDRAM device.
T_CKE
The T_CKE field fixes the minimum time between CKE transitions. This parameter is set to satisfy the
t
RAS
value for the attached SDRAM device.