20
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
31.4.66
CDMA Revision Identification Register (DMAREVID)
..................................................
31.4.67
CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)
................................
31.4.68
CDMA Emulation Control Register (DMAEMU)
.........................................................
31.4.69
CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3])
...............
31.4.70
CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3])
...............
31.4.71
CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]-
RXHPCRA[3])
...................................................................................................
31.4.72
CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]-
RXHPCRB[3])
...................................................................................................
31.4.73
CDMA Scheduler Control Register (DMA_SCHED_CTRL)
............................................
31.4.74
CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63])
...................................
31.4.75
Queue Manager Revision Identification Register (QMGRREVID)
....................................
31.4.76
Queue Manager Queue Diversion Register (DIVERSION)
............................................
31.4.77
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)
...................
31.4.78
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)
...................
31.4.79
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)
...................
31.4.80
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)
...................
31.4.81
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE)
..................
31.4.82
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)
..............................
31.4.83
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)
..................
31.4.84
Queue Manager Queue Pending Register 0 (PEND0)
.................................................
31.4.85
Queue Manager Queue Pending Register 1 (PEND1)
.................................................
31.4.86
Queue Manager Memory Region
R
Base Address Registers (QMEMRBASE[0]-
QMEMRBASE[15])
.............................................................................................
31.4.87
Queue Manager Memory Region
R
Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15])
...
31.4.88
Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63])
..............................
31.4.89
Queue Manager Queue
N
Status Register A (QSTATA[0]-QSTATA[63])
...........................
31.4.90
Queue Manager Queue
N
Status Register B (QSTATB[0]-QSTATB[63])
...........................
31.4.91
Queue Manager Queue
N
Status Register C (QSTATC[0]-QSTATC[63])
...........................
Revision History
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