8
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
16.6
Setting Up a Transfer
....................................................................................................
17
EMAC/MDIO Module
..........................................................................................................
17.1
Introduction
................................................................................................................
17.1.1
Purpose of the Peripheral
.....................................................................................
17.1.2
Features
..........................................................................................................
17.1.3
Functional Block Diagram
.....................................................................................
17.1.4
Industry Standard(s) Compliance Statement
................................................................
17.1.5
Terminology
.....................................................................................................
17.2
Architecture
................................................................................................................
17.2.1
Clock Control
....................................................................................................
17.2.2
Memory Map
....................................................................................................
17.2.3
Signal Descriptions
.............................................................................................
17.2.4
Ethernet Protocol Overview
...................................................................................
17.2.5
Programming Interface
.........................................................................................
17.2.6
EMAC Control Module
.........................................................................................
17.2.7
MDIO Module
...................................................................................................
17.2.8
EMAC Module
...................................................................................................
17.2.9
MAC Interface
...................................................................................................
17.2.10
Packet Receive Operation
...................................................................................
17.2.11
Packet Transmit Operation
..................................................................................
17.2.12
Receive and Transmit Latency
..............................................................................
17.2.13
Transfer Node Priority
........................................................................................
17.2.14
Reset Considerations
.........................................................................................
17.2.15
Initialization
.....................................................................................................
17.2.16
Interrupt Support
..............................................................................................
17.2.17
Power Management
..........................................................................................
17.2.18
Emulation Considerations
....................................................................................
17.3
Registers
...................................................................................................................
17.3.1
EMAC Control Module Registers
.............................................................................
17.3.2
MDIO Registers
.................................................................................................
17.3.3
EMAC Module Registers
.......................................................................................
18
External Memory Interface A (EMIFA)
..................................................................................
18.1
Introduction
................................................................................................................
18.1.1
Purpose of the Peripheral
.....................................................................................
18.1.2
Features
..........................................................................................................
18.1.3
Functional Block Diagram
.....................................................................................
18.2
Architecture
................................................................................................................
18.2.1
Clock Control
....................................................................................................
18.2.2
EMIFA Requests
................................................................................................
18.2.3
Pin Descriptions
.................................................................................................
18.2.4
SDRAM Controller and Interface
.............................................................................
18.2.5
Asynchronous Controller and Interface
......................................................................
18.2.6
Data Bus Parking
...............................................................................................
18.2.7
Reset and Initialization Considerations
......................................................................
18.2.8
Interrupt Support
................................................................................................
18.2.9
EDMA Event Support
..........................................................................................
18.2.10
Pin Multiplexing
................................................................................................
18.2.11
Memory Map
...................................................................................................
18.2.12
Priority and Arbitration
........................................................................................
18.2.13
System Considerations
.......................................................................................
18.2.14
Power Management
..........................................................................................
18.2.15
Emulation Considerations
....................................................................................
18.3
Example Configuration
...................................................................................................