Peripheral Clocking
113
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Device Clocking
(1)
See
for explanation of POSTDIV divider modes.
(2)
Certain PLL configurations do not support a 50 MHz clock on SYSCLK7.
Table 6-7. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Frequency (MHz)
Post Divider
Mode
(1)
POSTDIV Output
Frequency
PLLDIV7
Register Setting
SYSCLK7
25
24
600
Div2
300 MHz
5
50 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
25
18
450
Div2
225 MHz
Not Applicable
(2)
Div3
150 MHz
2
50 MHz
Div4
112.5 MHz
Not Applicable
(2)