13
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
24.1.8
Pin Data Clear Register (PDCLR)
..........................................................................
24.1.9
Global Control Register (GBLCTL)
.........................................................................
24.1.10
Audio Mute Control Register (AMUTE)
...................................................................
24.1.11
Digital Loopback Control Register (DLBCTL)
............................................................
24.1.12
Digital Mode Control Register (DITCTL)
..................................................................
24.1.13
Receiver Global Control Register (RGBLCTL)
...........................................................
24.1.14
Receive Format Unit Bit Mask Register (RMASK)
......................................................
24.1.15
Receive Bit Stream Format Register (RFMT)
............................................................
24.1.16
Receive Frame Sync Control Register (AFSRCTL)
.....................................................
24.1.17
Receive Clock Control Register (ACLKRCTL)
...........................................................
24.1.18
Receive High-Frequency Clock Control Register (AHCLKRCTL)
.....................................
24.1.19
Receive TDM Time Slot Register (RTDM)
...............................................................
24.1.20
Receiver Interrupt Control Register (RINTCTL)
.........................................................
24.1.21
Receiver Status Register (RSTAT)
........................................................................
24.1.22
Current Receive TDM Time Slot Registers (RSLOT)
...................................................
24.1.23
Receive Clock Check Control Register (RCLKCHK)
....................................................
24.1.24
Receiver DMA Event Control Register (REVTCTL)
.....................................................
24.1.25
Transmitter Global Control Register (XGBLCTL)
........................................................
24.1.26
Transmit Format Unit Bit Mask Register (XMASK)
......................................................
24.1.27
Transmit Bit Stream Format Register (XFMT)
...........................................................
24.1.28
Transmit Frame Sync Control Register (AFSXCTL)
....................................................
24.1.29
Transmit Clock Control Register (ACLKXCTL)
..........................................................
24.1.30
Transmit High-Frequency Clock Control Register (AHCLKXCTL)
....................................
24.1.31
Transmit TDM Time Slot Register (XTDM)
...............................................................
24.1.32
Transmitter Interrupt Control Register (XINTCTL)
......................................................
24.1.33
Transmitter Status Register (XSTAT)
.....................................................................
24.1.34
Current Transmit TDM Time Slot Register (XSLOT)
....................................................
24.1.35
Transmit Clock Check Control Register (XCLKCHK)
...................................................
24.1.36
Transmitter DMA Event Control Register (XEVTCTL)
..................................................
24.1.37
Serializer Control Registers (SRCTL
n
)
...................................................................
24.1.38
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
..........................................
24.1.39
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
........................................
24.1.40
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
.....................................
24.1.41
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
...................................
24.1.42
Transmit Buffer Registers (XBUF
n
)
.......................................................................
24.1.43
Receive Buffer Registers (RBUF
n
)
........................................................................
24.1.44
AFIFO Revision Identification Register (AFIFOREV)
...................................................
24.1.45
Write FIFO Control Register (WFIFOCTL)
...............................................................
24.1.46
Write FIFO Status Register (WFIFOSTS)
................................................................
24.1.47
Read FIFO Control Register (RFIFOCTL)
................................................................
24.1.48
Read FIFO Status Register (RFIFOSTS)
.................................................................
25
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
.................................................
25.1
Introduction
...............................................................................................................
25.1.1
Purpose of the Peripheral
....................................................................................
25.1.2
Features
........................................................................................................
25.1.3
Functional Block Diagram
....................................................................................
25.1.4
Supported Use Case Statement
............................................................................
25.1.5
Industry Standard(s) Compliance Statement
..............................................................
25.2
Architecture
..............................................................................................................
25.2.1
Clock Control
..................................................................................................
25.2.2
Signal Descriptions
............................................................................................
25.2.3
Protocol Descriptions
.........................................................................................
25.2.4
Data Flow in the Input/Output FIFO
........................................................................