9
SPRUH91D – March 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
18.3.1
Hardware Interface
.............................................................................................
18.3.2
Software Configuration
.........................................................................................
18.4
Registers
...................................................................................................................
18.4.1
Module ID Register (MIDR)
...................................................................................
18.4.2
Asynchronous Wait Cycle Configuration Register (AWCC)
...............................................
18.4.3
SDRAM Configuration Register (SDCR)
....................................................................
18.4.4
SDRAM Refresh Control Register (SDRCR)
................................................................
18.4.5
Asynchronous
n
Configuration Registers (CE2CFG-CE5CFG)
..........................................
18.4.6
SDRAM Timing Register (SDTIMR)
..........................................................................
18.4.7
SDRAM Self Refresh Exit Timing Register (SDSRETR)
..................................................
18.4.8
EMIFA Interrupt Raw Register (INTRAW)
...................................................................
18.4.9
EMIFA Interrupt Masked Register (INTMSK)
...............................................................
18.4.10
EMIFA Interrupt Mask Set Register (INTMSKSET)
.......................................................
18.4.11
EMIFA Interrupt Mask Clear Register (INTMSKCLR)
....................................................
18.4.12
NAND Flash Control Register (NANDFCR)
...............................................................
18.4.13
NAND Flash Status Register (NANDFSR)
.................................................................
18.4.14
NAND Flash
n
ECC Registers (NANDF1ECC-NANDF4ECC)
..........................................
18.4.15
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)
.......................................
18.4.16
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1)
..................................................
18.4.17
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2)
..................................................
18.4.18
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3)
..................................................
18.4.19
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4)
..................................................
18.4.20
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1)
.................................
18.4.21
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)
.................................
18.4.22
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)
.....................................
18.4.23
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)
.....................................
19
External Memory Interface B (EMIFB)
..................................................................................
19.1
Introduction
................................................................................................................
19.1.1
Purpose of the Peripheral
.....................................................................................
19.1.2
Features
..........................................................................................................
19.1.3
Functional Block Diagram
.....................................................................................
19.2
Architecture
................................................................................................................
19.2.1
Clock Control
....................................................................................................
19.2.2
EMIF Requests
..................................................................................................
19.2.3
Pin Descriptions
.................................................................................................
19.2.4
Pin Multiplexing
.................................................................................................
19.2.5
Memory Map
....................................................................................................
19.2.6
SDRAM Controller and Interface
.............................................................................
19.2.7
Reset and Initialization Considerations
......................................................................
19.2.8
Interrupt Support
................................................................................................
19.2.9
Power Management
............................................................................................
19.2.10
Emulation Considerations
....................................................................................
19.3
Example Configuration
...................................................................................................
19.4
Registers
...................................................................................................................
19.4.1
SDRAM Configuration Register (SDCFG)
..................................................................
19.4.2
SDRAM Refresh Control Register (SDRFC)
................................................................
19.4.3
SDRAM Timing 1 Register (SDTIM1)
........................................................................
19.4.4
SDRAM Timing 2 Register (SDTIM2)
........................................................................
19.4.5
Peripheral Bus Burst Priority Register (BPRIO)
............................................................
19.4.6
Performance Counter 1 Register (PC1)
.....................................................................
19.4.7
Performance Counter 2 Register (PC2)
.....................................................................
19.4.8
Performance Counter Configuration Register (PCC)
......................................................
19.4.9
Performance Counter Master Region Select Register (PCMRS)
........................................